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From: "rguenth at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug tree-optimization/105394] [12 Regression] ICE: verify_gimple
 failed with MVE during GIMPLE pass: veclower2
Date: Tue, 26 Apr 2022 12:40:25 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105394

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |rguenth at gcc dot =
gnu.org
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2022-04-26
             Status|UNCONFIRMED                 |ASSIGNED

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Hmm, in my cross-arm build I get

> ./cc1plus -quiet t.c -I include -march=3Darmv8.1-m.main+mve -mfloat-abi=
=3Dhard -O
cc1plus: error: target CPU does not support ARM mode

while in my cross-aarch64 build:

> ./cc1plus -quiet t.c -I include -march=3Darmv8.1-m.main+mve -mfloat-abi=
=3Dhard -O
cc1plus: error: unrecognized command-line option '-mfloat-abi=3Dhard'
cc1plus: error: unknown value 'armv8.1-m.main+mve' for '-march'
cc1plus: note: valid arguments are: armv8-a armv8.1-a armv8.2-a armv8.3-a
armv8.4-a armv8.5-a armv8.6-a armv8.7-a armv8.8-a armv8-r armv9-a

in the cross-arm build adding -mthumb reproduces the ICE, I guess my
configury (--target=3Darm-none-linux-gnueabihf --with-float=3Dhard
--with-cpu=3Dcortex-a9 --with-fpu=3Dneon-fp16) plays a role here.

I will have a look.=