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From: "egallager at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/105504] Fails to break dependency for vcvtss2sd xmm,
 xmm, mem
Date: Sat, 05 Aug 2023 15:05:41 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105504

--- Comment #7 from Eric Gallager <egallager at gcc dot gnu.org> ---
(In reply to CVS Commits from comment #6)
> The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
>=20
> https://gcc.gnu.org/g:5e005393d4ff0a428c5f55b9ba7f65d6078a7cf5
>=20
> commit r13-1009-g5e005393d4ff0a428c5f55b9ba7f65d6078a7cf5
> Author: liuhongt <hongtao.liu@intel.com>
> Date:   Mon May 30 15:30:51 2022 +0800
>=20
>     Disparages SSE_REGS alternatives sligntly with ?v instead of *v in
> *mov{si,di}_internal.
>=20=20=20=20=20
>     So alternative v won't be igored in record_reg_classess.
>=20=20=20=20=20
>     Similar for *r alternatives in some vector patterns.
>=20=20=20=20=20
>     It helps testcase in the PR, also RA now makes better decisions for
>     gcc.target/i386/extract-insert-combining.c
>=20=20=20=20=20
>             movd    %esi, %xmm0
>             movd    %edi, %xmm1
>     -       movl    %esi, -12(%rsp)
>             paddd   %xmm0, %xmm1
>             pinsrd  $0, %esi, %xmm0
>             paddd   %xmm1, %xmm0
>=20=20=20=20=20
>     The patch has no big impact on SPEC2017 for both O2 and Ofast
>     march=3Dnative run.
>=20=20=20=20=20
>     And I noticed there's some changes in SPEC2017 from code like
>=20=20=20=20=20
>     mov mem, %eax
>     vmovd %eax, %xmm0
>     ..
>     mov %eax, 64(%rsp)
>=20=20=20=20=20
>     to
>=20=20=20=20=20
>     vmovd mem, %xmm0
>     ..
>     vmovd %xmm0, 64(%rsp)
>=20=20=20=20=20
>     Which should be exactly what we want?
>=20=20=20=20=20
>     gcc/ChangeLog:
>=20=20=20=20=20
>             PR target/105513
>             PR target/105504
>             * config/i386/i386.md (*movsi_internal): Change alternative
>             from *v to ?v.
>             (*movdi_internal): Ditto.
>             * config/i386/sse.md (vec_set<mode>_0): Change alternative *r
>             to ?r.
>             (*vec_extractv4sf_mem): Ditto.
>             (*vec_extracthf): Ditto.
>=20=20=20=20=20
>     gcc/testsuite/ChangeLog:
>=20=20=20=20=20
>             * gcc.target/i386/pr105513-1.c: New test.
>             * gcc.target/i386/extract-insert-combining.c: Add new
>             scan-assembler-not for spill.

Did this fix it?=