From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id EDADC385355A; Wed, 8 Jun 2022 03:24:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EDADC385355A From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105513] [10/11/12/13 Regression] Unnecessary SSE spill since r9-5748-g1d4b4f4979171ef0 Date: Wed, 08 Jun 2022 03:24:53 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.1.0 X-Bugzilla-Keywords: missed-optimization, ra X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 10.4 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Jun 2022 03:24:54 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105513 --- Comment #10 from CVS Commits --- The master branch has been updated by hongtao Liu : https://gcc.gnu.org/g:5e005393d4ff0a428c5f55b9ba7f65d6078a7cf5 commit r13-1009-g5e005393d4ff0a428c5f55b9ba7f65d6078a7cf5 Author: liuhongt Date: Mon May 30 15:30:51 2022 +0800 Disparages SSE_REGS alternatives sligntly with ?v instead of *v in *mov{si,di}_internal. So alternative v won't be igored in record_reg_classess. Similar for *r alternatives in some vector patterns. It helps testcase in the PR, also RA now makes better decisions for gcc.target/i386/extract-insert-combining.c movd %esi, %xmm0 movd %edi, %xmm1 - movl %esi, -12(%rsp) paddd %xmm0, %xmm1 pinsrd $0, %esi, %xmm0 paddd %xmm1, %xmm0 The patch has no big impact on SPEC2017 for both O2 and Ofast march=3Dnative run. And I noticed there's some changes in SPEC2017 from code like mov mem, %eax vmovd %eax, %xmm0 .. mov %eax, 64(%rsp) to vmovd mem, %xmm0 .. vmovd %xmm0, 64(%rsp) Which should be exactly what we want? gcc/ChangeLog: PR target/105513 PR target/105504 * config/i386/i386.md (*movsi_internal): Change alternative from *v to ?v. (*movdi_internal): Ditto. * config/i386/sse.md (vec_set_0): Change alternative *r to ?r. (*vec_extractv4sf_mem): Ditto. (*vec_extracthf): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr105513-1.c: New test. * gcc.target/i386/extract-insert-combining.c: Add new scan-assembler-not for spill.=