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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV instructions
Date: Tue, 24 May 2022 16:12:53 +0000	[thread overview]
Message-ID: <bug-105666-4-OBstvPjkHo@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-105666-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

Vineet Gupta <vineet.gupta at linux dot dev> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Commited by Kito.

commit b646d7d279ae0c0d35564542d09866bf3e8afac0
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Mon May 23 11:12:09 2022 -0700

    RISC-V: Inhibit FP <--> int register moves via tune param

    Under extreme register pressure, compiler can use FP <--> int
    moves as a cheap alternate to spilling to memory.
    This was seen with SPEC2017 FP benchmark 507.cactu:
    ML_BSSN_Advect.cc:ML_BSSN_Advect_Body()

      parent reply	other threads:[~2022-05-24 16:12 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-19 22:33 [Bug target/105666] New: " vineet.gupta at linux dot dev
2022-05-19 22:45 ` [Bug target/105666] " vineet.gupta at linux dot dev
2022-05-19 22:51 ` pinskia at gcc dot gnu.org
2022-05-23 19:35 ` vineet.gupta at linux dot dev
2022-05-24 16:12 ` vineet.gupta at linux dot dev [this message]

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