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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV
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Date: Tue, 24 May 2022 16:12:53 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105666

Vineet Gupta <vineet.gupta at linux dot dev> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Commited by Kito.

commit b646d7d279ae0c0d35564542d09866bf3e8afac0
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Mon May 23 11:12:09 2022 -0700

    RISC-V: Inhibit FP <--> int register moves via tune param

    Under extreme register pressure, compiler can use FP <--> int
    moves as a cheap alternate to spilling to memory.
    This was seen with SPEC2017 FP benchmark 507.cactu:
    ML_BSSN_Advect.cc:ML_BSSN_Advect_Body()=