[Bug target/105666] New: RISC-V 507.cactuBSSN_r build has costly FMV instructions

[Bug target/105666] New: RISC-V 507.cactuBSSN_r build has costly FMV instructions

[vineet.gupta at linux dot dev]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

            Bug ID: 105666
           Summary: RISC-V 507.cactuBSSN_r build has costly FMV
                    instructions
           Product: gcc
           Version: 12.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: vineet.gupta at linux dot dev
  Target Milestone: ---

Created attachment 53001
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53001&action=edit
Test case to generate FMV.d.x instructions

SPEC2017 FP benchmark 507.cactu: ML_BSSN_Advect.cc:ML_BSSN_Advect_Body() has
really ugly code causing high register pressure and ensuing spills of both FP
and int register. Current riscv TARGET_REGISTER_MOVE_COST lacking any cost
considerations, resorts to fp <--> int mov as opposed to spilling to stack.

    |       fmv.d.x fa5,s9  # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1
    | .LVL325:
    |       ld      s9,184(sp)              # _12469, %sfp
    | ...
    | .LVL339:
    |       fmv.x.d s4,fa5  # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1

The FMV.d.x / FMV.x.d instructions could be costly on certain
micro-architectures and thus needs to be made tunable.

Test case attached: ripped off of existing
gcc/testsuite/gcc.c-torture/execute/pr28982a.c

[Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV instructions

[vineet.gupta at linux dot dev]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

Vineet Gupta <vineet.gupta at linux dot dev> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vineet.gupta at linux dot dev

--- Comment #1 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Created attachment 53002
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53002&action=edit
proposed fix

[Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV instructions

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Patches should be set to gcc-patches after reading
https://gcc.gnu.org/contribute.html

[Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV instructions

[vineet.gupta at linux dot dev]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

--- Comment #3 from Vineet Gupta <vineet.gupta at linux dot dev> ---
https://gcc.gnu.org/pipermail/gcc-patches/2022-May/595428.html

[Bug target/105666] RISC-V 507.cactuBSSN_r build has costly FMV instructions

[vineet.gupta at linux dot dev]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666

Vineet Gupta <vineet.gupta at linux dot dev> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #4 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Commited by Kito.

commit b646d7d279ae0c0d35564542d09866bf3e8afac0
Author: Vineet Gupta <vineetg@rivosinc.com>
Date:   Mon May 23 11:12:09 2022 -0700

    RISC-V: Inhibit FP <--> int register moves via tune param

    Under extreme register pressure, compiler can use FP <--> int
    moves as a cheap alternate to spilling to memory.
    This was seen with SPEC2017 FP benchmark 507.cactu:
    ML_BSSN_Advect.cc:ML_BSSN_Advect_Body()