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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/105666] New: RISC-V 507.cactuBSSN_r build has costly FMV instructions
Date: Thu, 19 May 2022 22:33:33 +0000 [thread overview]
Message-ID: <bug-105666-4@http.gcc.gnu.org/bugzilla/> (raw)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105666
Bug ID: 105666
Summary: RISC-V 507.cactuBSSN_r build has costly FMV
instructions
Product: gcc
Version: 12.1.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: vineet.gupta at linux dot dev
Target Milestone: ---
Created attachment 53001
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53001&action=edit
Test case to generate FMV.d.x instructions
SPEC2017 FP benchmark 507.cactu: ML_BSSN_Advect.cc:ML_BSSN_Advect_Body() has
really ugly code causing high register pressure and ensuing spills of both FP
and int register. Current riscv TARGET_REGISTER_MOVE_COST lacking any cost
considerations, resorts to fp <--> int mov as opposed to spilling to stack.
| fmv.d.x fa5,s9 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1
| .LVL325:
| ld s9,184(sp) # _12469, %sfp
| ...
| .LVL339:
| fmv.x.d s4,fa5 # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1
The FMV.d.x / FMV.x.d instructions could be costly on certain
micro-architectures and thus needs to be made tunable.
Test case attached: ripped off of existing
gcc/testsuite/gcc.c-torture/execute/pr28982a.c
next reply other threads:[~2022-05-19 22:33 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-19 22:33 vineet.gupta at linux dot dev [this message]
2022-05-19 22:45 ` [Bug target/105666] " vineet.gupta at linux dot dev
2022-05-19 22:51 ` pinskia at gcc dot gnu.org
2022-05-23 19:35 ` vineet.gupta at linux dot dev
2022-05-24 16:12 ` vineet.gupta at linux dot dev
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