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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/105666] New: RISC-V 507.cactuBSSN_r build has costly FMV
 instructions
Date: Thu, 19 May 2022 22:33:33 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105666

            Bug ID: 105666
           Summary: RISC-V 507.cactuBSSN_r build has costly FMV
                    instructions
           Product: gcc
           Version: 12.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: vineet.gupta at linux dot dev
  Target Milestone: ---

Created attachment 53001
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=3D53001&action=3Dedit
Test case to generate FMV.d.x instructions

SPEC2017 FP benchmark 507.cactu: ML_BSSN_Advect.cc:ML_BSSN_Advect_Body() has
really ugly code causing high register pressure and ensuing spills of both =
FP
and int register. Current riscv TARGET_REGISTER_MOVE_COST lacking any cost
considerations, resorts to fp <--> int mov as opposed to spilling to stack.

    |       fmv.d.x fa5,s9  # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1
    | .LVL325:
    |       ld      s9,184(sp)              # _12469, %sfp
    | ...
    | .LVL339:
    |       fmv.x.d s4,fa5  # PDupwindNthSymm2Xt1, PDupwindNthSymm2Xt1

The FMV.d.x / FMV.x.d instructions could be costly on certain
micro-architectures and thus needs to be made tunable.

Test case attached: ripped off of existing
gcc/testsuite/gcc.c-torture/execute/pr28982a.c=