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From: "linkw at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/105744] [11/12/13 Regression] wrong code with -fexpensive-optimizations -flive-range-shrinkage on powerpc64le-unknown-linux-gnu
Date: Fri, 27 May 2022 07:47:48 +0000 [thread overview]
Message-ID: <bug-105744-4-NkZgNByfdN@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-105744-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105744
--- Comment #2 from Kewen Lin <linkw at gcc dot gnu.org> ---
This exposes one bug in glibc strncpy power9 implementation
In
https://sourceware.org/git/?p=glibc.git;a=blob_plain;f=sysdeps/powerpc/powerpc64/le/power9/strncpy.S
lbz r0,0(r4)
stb r0,0(r3)
addi r11,r3,1
addi r5,r5,-1
vspltisb v18,0 /* Zeroes in v18 */
...
L(zero_padding_end):
sldi r10,r5,56 /* stxvl wants size in top 8 bits */
stxvl v18,r11,r10 /* Partial store */
blr
The code at label "zero_padding_end" is supposed to use v18, but the stxvl will
take the 18 as vsx No. instead of vr No, so it ends up to use the wrong
register vs18 instead of v18 for the store.
The reason why the optimization option matters is that some optimization happen
to generate some sequence to modify the value of vs18 then it's not expected to
be zero any more.
next prev parent reply other threads:[~2022-05-27 7:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-26 18:08 [Bug rtl-optimization/105744] New: " zsojka at seznam dot cz
2022-05-27 6:31 ` [Bug rtl-optimization/105744] " rguenth at gcc dot gnu.org
2022-05-27 7:12 ` linkw at gcc dot gnu.org
2022-05-27 7:47 ` linkw at gcc dot gnu.org [this message]
2022-05-27 7:55 ` linkw at gcc dot gnu.org
2022-05-27 8:09 ` zsojka at seznam dot cz
2022-05-27 8:23 ` linkw at gcc dot gnu.org
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