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From: "linkw at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug rtl-optimization/105744] [11/12/13 Regression] wrong code with
 -fexpensive-optimizations -flive-range-shrinkage on
 powerpc64le-unknown-linux-gnu
Date: Fri, 27 May 2022 07:47:48 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105744

--- Comment #2 from Kewen Lin <linkw at gcc dot gnu.org> ---
This exposes one bug in glibc strncpy power9 implementation

In
https://sourceware.org/git/?p=3Dglibc.git;a=3Dblob_plain;f=3Dsysdeps/powerp=
c/powerpc64/le/power9/strncpy.S

        lbz     r0,0(r4)
        stb     r0,0(r3)
        addi    r11,r3,1
        addi    r5,r5,-1
        vspltisb v18,0          /* Zeroes in v18  */

...

L(zero_padding_end):
        sldi    r10,r5,56       /* stxvl wants size in top 8 bits  */
        stxvl   v18,r11,r10     /* Partial store  */
        blr

The code at label "zero_padding_end" is supposed to use v18, but the stxvl =
will
take the 18 as vsx No. instead of vr No, so it ends up to use the wrong
register vs18 instead of v18 for the store.

The reason why the optimization option matters is that some optimization ha=
ppen
to generate some sequence to modify the value of vs18 then it's not expecte=
d to
be zero any more.=