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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/105773] [Aarch64] Failure to optimize and+cmp to tst
Date: Thu, 13 Oct 2022 13:56:41 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105773

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Wilco Dijkstra <wilco@gcc.gnu.org>:

https://gcc.gnu.org/g:1cccf644ff92ac1145abdbf255d1862dd787875b

commit r13-3274-g1cccf644ff92ac1145abdbf255d1862dd787875b
Author: Wilco Dijkstra <wdijkstr@arm.com>
Date:   Thu Oct 13 14:41:55 2022 +0100

    [AArch64] Improve bit tests [PR105773]

    Since AArch64 sets all flags on logical operations, comparisons with ze=
ro
    can be combined into an AND even if the condition is LE or GT. Add a new
    CC_NZV mode used by ANDS/BICS/TST instructions.

    gcc/
            PR target/105773
            * config/aarch64/aarch64.cc (aarch64_select_cc_mode): Allow
            GT/LE for merging compare with zero into AND.
            (aarch64_get_condition_code_1): Add CC_NZVmode support.
            * config/aarch64/aarch64-modes.def: Add CC_NZV.
            * config/aarch64/aarch64.md: Use CC_NZV in cmp+and patterns.

    gcc/testsuite/
            PR target/105773
            * gcc.target/aarch64/ands_2.c: Test for ANDS.
            * gcc.target/aarch64/bics_2.c: Test for BICS.
            * gcc.target/aarch64/tst_2.c: Test for TST.
            * gcc.target/aarch64/tst_imm_split_1.c: Fix test.=