From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 6E657384F01C; Mon, 30 May 2022 22:42:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 6E657384F01C From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105778] Shift by register --- unnecessary AND instruction Date: Mon, 30 May 2022 22:42:52 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.1.0 X-Bugzilla-Keywords: X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 May 2022 22:42:52 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105778 Jakub Jelinek changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org --- Comment #1 from Jakub Jelinek --- I think: --- gcc/config/i386/i386.md.jj 2022-05-30 14:07:11.988199636 +0200 +++ gcc/config/i386/i386.md 2022-05-31 00:39:08.031757037 +0200 @@ -12708,19 +12708,21 @@ (define_expand "3" "" "ix86_expand_binary_operator (, mode, operands); DONE;") +(define_mode_iterator SWI48A [SI (DI "TARGET_64BIT")]) + ;; Avoid useless masking of count operand. -(define_insn_and_split "*3_mask" +(define_insn_and_split "*3_mask_" [(set (match_operand:SWI48 0 "nonimmediate_operand") (any_shiftrt:SWI48 (match_operand:SWI48 1 "nonimmediate_operand") (subreg:QI - (and:SI - (match_operand:SI 2 "register_operand" "c,r") - (match_operand:SI 3 "const_int_operand")) 0))) + (and:SWI48A + (match_operand:SWI48A 2 "register_operand" "c,r") + (match_operand:SWI48A 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] - "ix86_binary_operator_ok (, mode, operands) - && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) - =3D=3D GET_MODE_BITSIZE (mode)-1 + "ix86_binary_operator_ok (, mode, operands) + && (INTVAL (operands[3]) & (GET_MODE_BITSIZE (mode)-1)) + =3D=3D GET_MODE_BITSIZE (mode)-1 && ix86_pre_reload_split ()" "#" "&& 1" @@ -12754,16 +12756,16 @@ (define_insn_and_split "*3_m "" [(set_attr "isa" "*,bmi2")]) -(define_insn_and_split "*3_doubleword_mask" - [(set (match_operand: 0 "register_operand") - (any_shiftrt: - (match_operand: 1 "register_operand") +(define_insn_and_split "*3_doubleword_mask_" + [(set (match_operand: 0 "register_operand") + (any_shiftrt: + (match_operand: 1 "register_operand") (subreg:QI - (and:SI - (match_operand:SI 2 "register_operand" "c") - (match_operand:SI 3 "const_int_operand")) 0))) + (and:SWI48 + (match_operand:SWI48 2 "register_operand" "c") + (match_operand:SWI48 3 "const_int_operand")) 0))) (clobber (reg:CC FLAGS_REG))] - "(INTVAL (operands[3]) & ( * BITS_PER_UNIT)) =3D=3D 0 + "(INTVAL (operands[3]) & ( * BITS_PER_UNIT)) =3D=3D 0 && ix86_pre_reload_split ()" "#" "&& 1" @@ -12772,7 +12774,8 @@ (define_insn_and_split "*3_do (ior:DWIH (lshiftrt:DWIH (match_dup 4) (and:QI (match_dup 2) (match_dup 8))) (subreg:DWIH - (ashift: (zero_extend: (match_dup 7)) + (ashift: + (zero_extend: (match_dup 7)) (minus:QI (match_dup 9) (and:QI (match_dup 2) (match_dup 8)))) 0= ))) (clobber (reg:CC FLAGS_REG))]) @@ -12781,13 +12784,14 @@ (define_insn_and_split "*3_do (any_shiftrt:DWIH (match_dup 7) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] { - split_double_mode (mode, &operands[0], 2, &operands[4], &operands[6= ]); + split_double_mode (mode, &operands[0], 2, &operands[4], + &operands[6]); - operands[8] =3D GEN_INT ( * BITS_PER_UNIT - 1); - operands[9] =3D GEN_INT ( * BITS_PER_UNIT); + operands[8] =3D GEN_INT ( * BITS_PER_UNIT - 1); + operands[9] =3D GEN_INT ( * BITS_PER_UNIT); - if ((INTVAL (operands[3]) & (( * BITS_PER_UNIT) - 1)) - !=3D (( * BITS_PER_UNIT) - 1)) + if ((INTVAL (operands[3]) & (( * BITS_PER_UNIT) - 1)) + !=3D (( * BITS_PER_UNIT) - 1)) { rtx tem =3D gen_reg_rtx (SImode); emit_insn (gen_andsi3 (tem, operands[2], operands[3])); could fix this. Wonder if it couldn't be written without the extra iterator though...=