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From: "jcmvbkbc at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105879] New: DI mode constants are incorrectly loaded into registers on big-endian xtensa Date: Wed, 08 Jun 2022 04:07:52 +0000 [thread overview] Message-ID: <bug-105879-4@http.gcc.gnu.org/bugzilla/> (raw) https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105879 Bug ID: 105879 Summary: DI mode constants are incorrectly loaded into registers on big-endian xtensa Product: gcc Version: 13.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: jcmvbkbc at gcc dot gnu.org Target Milestone: --- A lot of testsuite tests are failing in big-endian xtensa configuration, e.g. gcc.c-torture/execute/20001031-1.c For the following part long long t4 (void) { long long i; t3 ((i = 4096) + 0x7fffffffULL); return i; } in the generated assembly I see the following: .literal .LC7, -2147479553 .literal .LC8, t3@PLT .literal .LC9, 4096 .align 4 .global t4 .type t4, @function t4: entry sp, 32 movi.n a3, 0 l32r a10, .LC7 mov.n a11, a3 l32r a8, .LC8 callx8 a8 l32r a2, .LC9 retw.n (i.e. 0 in a11), while it should've been the following (i.e. 0 in a10): .literal .LC7, -2147479553 .literal .LC8, t3@PLT .literal .LC9, 4096 .align 4 .global t4 .type t4, @function t4: entry sp, 32 movi.n a2, 0 mov.n a10, a2 l32r a11, .LC7 l32r a8, .LC8 callx8 a8 l32r a3, .LC9 retw.n This regression clearly traces back to the commit 64a54505ec82 ("gcc: xtensa: rearrange DI mode constant loading") and is present in gcc-11.1+ and gcc-12.1
next reply other threads:[~2022-06-08 4:07 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-08 4:07 jcmvbkbc at gcc dot gnu.org [this message] 2022-06-08 4:27 ` [Bug target/105879] " jcmvbkbc at gcc dot gnu.org 2022-06-08 15:48 ` cvs-commit at gcc dot gnu.org 2022-06-08 16:17 ` cvs-commit at gcc dot gnu.org 2022-06-08 16:25 ` cvs-commit at gcc dot gnu.org 2022-06-08 16:27 ` jcmvbkbc at gcc dot gnu.org
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