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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/105911] [13 Regression] ICE: in extract_insn, at recog.cc:2791 (error: unrecognizable insn)
Date: Mon, 13 Jun 2022 08:54:37 +0000 [thread overview]
Message-ID: <bug-105911-4-plcMSv8scj@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-105911-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105911
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:
https://gcc.gnu.org/g:13ea4a6e830da1f245136601e636dec62e74d1a7
commit r13-1061-g13ea4a6e830da1f245136601e636dec62e74d1a7
Author: Jakub Jelinek <jakub@redhat.com>
Date: Mon Jun 13 10:53:33 2022 +0200
i386: Fix up *<dwi>3_doubleword_mask [PR105911]
Another regression caused by my recent patch.
This time because define_insn_and_split only requires that the
constant mask is const_int_operand. When it was only SImode,
that wasn't a problem, HImode neither, but for DImode if we need
to and the shift count we might run into a problem that it isn't
a representable signed 32-bit immediate.
But, we don't really care about the upper bits of the mask, so
we can just mask the CONST_INT with the mode mask.
2022-06-13 Jakub Jelinek <jakub@redhat.com>
PR target/105911
* config/i386/i386.md (*ashl<dwi>3_doubleword_mask,
*<insn><dwi>3_doubleword_mask): Use operands[3] masked with
(<MODE_SIZE> * BITS_PER_UNIT) - 1 as AND operand instead of
operands[3] unmodified.
* gcc.dg/pr105911.c: New test.
next prev parent reply other threads:[~2022-06-13 8:54 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-09 17:31 [Bug target/105911] New: " asolokha at gmx dot com
2022-06-09 18:00 ` [Bug target/105911] " jakub at gcc dot gnu.org
2022-06-10 10:34 ` jakub at gcc dot gnu.org
2022-06-13 8:54 ` cvs-commit at gcc dot gnu.org [this message]
2022-06-13 9:04 ` jakub at gcc dot gnu.org
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