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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) Date: Mon, 18 Sep 2023 12:28:13 +0000 [thread overview] Message-ID: <bug-105928-4-JrItw2TvFR@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-105928-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 --- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Wilco Dijkstra <wilco@gcc.gnu.org>: https://gcc.gnu.org/g:fc7070025d1a6668ff6cb4391f84771a7662def7 commit r14-4096-gfc7070025d1a6668ff6cb4391f84771a7662def7 Author: Wilco Dijkstra <wilco.dijkstra@arm.com> Date: Wed Sep 13 13:21:50 2023 +0100 AArch64: Improve immediate expansion [PR105928] Support immediate expansion of immediates which can be created from 2 MOVKs and a shifted ORR or BIC instruction. Change aarch64_split_dimode_const_store to apply if we save one instruction. This reduces the number of 4-instruction immediates in SPECINT/FP by 5%. gcc/ChangeLog: PR target/105928 * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate) Add support for immediates using shifted ORR/BIC. (aarch64_split_dimode_const_store): Apply if we save one instruction. * config/aarch64/aarch64.md (<LOGICAL:optab>_<SHIFT:optab><mode>3): Make pattern global. gcc/testsuite: PR target/105928 * gcc.target/aarch64/pr105928.c: Add new test. * gcc.target/aarch64/vect-cse-codegen.c: Fix test.
next prev parent reply other threads:[~2023-09-18 12:28 UTC|newest] Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-11 20:19 [Bug target/105928] New: " peter at cordes dot ca 2022-07-05 11:48 ` [Bug target/105928] " rsandifo at gcc dot gnu.org 2023-09-13 13:08 ` wilco at gcc dot gnu.org 2023-09-14 15:26 ` wilco at gcc dot gnu.org 2023-09-18 12:28 ` cvs-commit at gcc dot gnu.org [this message] 2023-09-18 12:33 ` wilco at gcc dot gnu.org
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