From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 4888C3858D3C; Wed, 13 Sep 2023 13:08:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 4888C3858D3C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1694610539; bh=2Swl6qNVOiw5JPHx0wQ46R8igAhg0jkX3G9lHemzWZ8=; h=From:To:Subject:Date:In-Reply-To:References:From; b=lKbidKz1Oij3nzEMmL+SGYv+D27nFCWTju4ZoywZuZxPi16dl0DmnyMx2/kCkGhfM YVI2jTqMazwFAb2OhzidgSzKzbHVEEVS3pEzeWKbF+aDnql+aTjeacGPxO2vN80fmX 1EKjcnJGrOzM1CEWDXHT/4AVih4r7ry4R/OYrQNE= From: "wilco at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) Date: Wed, 13 Sep 2023 13:08:58 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: wilco at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: wilco at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc assigned_to Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D105928 Wilco changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |wilco at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |wilco at gcc dot gn= u.org --- Comment #2 from Wilco --- Shifted logical operations are single cycle on all recent cores.=