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* [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) @ 2022-06-11 20:19 peter at cordes dot ca 2022-07-05 11:48 ` [Bug target/105928] " rsandifo at gcc dot gnu.org ` (4 more replies) 0 siblings, 5 replies; 6+ messages in thread From: peter at cordes dot ca @ 2022-06-11 20:19 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 Bug ID: 105928 Summary: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) Product: gcc Version: 13.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: normal Priority: P3 Component: target Assignee: unassigned at gcc dot gnu.org Reporter: peter at cordes dot ca Target Milestone: --- Target: arm64-*-* void foo(unsigned long *p) { *p = 0xdeadbeefdeadbeef; } cleverly compiles to https://godbolt.org/z/b3oqao5Kz mov w1, 48879 movk w1, 0xdead, lsl 16 stp w1, w1, [x0] ret But producing the value in a register uses more than 3 instructions: unsigned long constant(){ return 0xdeadbeefdeadbeef; } mov x0, 48879 movk x0, 0xdead, lsl 16 movk x0, 0xbeef, lsl 32 movk x0, 0xdead, lsl 48 ret At least with -Os, and maybe at -O2 or -O3 if it's efficient, we could be doing a shifted ADD or ORR to broadcast a zero-extended 32-bit value to 64-bit. mov x0, 48879 movk x0, 0xdead, lsl 16 add x0, x0, x0, lsl 32 Some CPUs may fuse sequences of movk, and shifted operands for ALU ops may take extra time in some CPUs, so this might not actually be optimal for performance, but it is smaller for -Os and -Oz. We should also be using that trick for stores to _Atomic or volatile long*, where we currently do MOV + 3x MOVK, then an STR, with ARMv8.4-a which guarantees atomicity. --- ARMv8.4-a and later guarantees atomicity for ldp/stp within an aligned 16-byte chunk, so we should use MOV/MOVK / STP there even for volatile or __ATOMIC_RELAXED. But presumably that's a different part of GCC's internals, so I'll report that separately. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca @ 2022-07-05 11:48 ` rsandifo at gcc dot gnu.org 2023-09-13 13:08 ` wilco at gcc dot gnu.org ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: rsandifo at gcc dot gnu.org @ 2022-07-05 11:48 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 CC| |rsandifo at gcc dot gnu.org Last reconfirmed| |2022-07-05 Status|UNCONFIRMED |NEW --- Comment #1 from rsandifo at gcc dot gnu.org <rsandifo at gcc dot gnu.org> --- Confirmed. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca 2022-07-05 11:48 ` [Bug target/105928] " rsandifo at gcc dot gnu.org @ 2023-09-13 13:08 ` wilco at gcc dot gnu.org 2023-09-14 15:26 ` wilco at gcc dot gnu.org ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: wilco at gcc dot gnu.org @ 2023-09-13 13:08 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |wilco at gcc dot gnu.org Assignee|unassigned at gcc dot gnu.org |wilco at gcc dot gnu.org --- Comment #2 from Wilco <wilco at gcc dot gnu.org> --- Shifted logical operations are single cycle on all recent cores. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca 2022-07-05 11:48 ` [Bug target/105928] " rsandifo at gcc dot gnu.org 2023-09-13 13:08 ` wilco at gcc dot gnu.org @ 2023-09-14 15:26 ` wilco at gcc dot gnu.org 2023-09-18 12:28 ` cvs-commit at gcc dot gnu.org 2023-09-18 12:33 ` wilco at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: wilco at gcc dot gnu.org @ 2023-09-14 15:26 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 --- Comment #3 from Wilco <wilco at gcc dot gnu.org> --- Patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-September/630358.html ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca ` (2 preceding siblings ...) 2023-09-14 15:26 ` wilco at gcc dot gnu.org @ 2023-09-18 12:28 ` cvs-commit at gcc dot gnu.org 2023-09-18 12:33 ` wilco at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: cvs-commit at gcc dot gnu.org @ 2023-09-18 12:28 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 --- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Wilco Dijkstra <wilco@gcc.gnu.org>: https://gcc.gnu.org/g:fc7070025d1a6668ff6cb4391f84771a7662def7 commit r14-4096-gfc7070025d1a6668ff6cb4391f84771a7662def7 Author: Wilco Dijkstra <wilco.dijkstra@arm.com> Date: Wed Sep 13 13:21:50 2023 +0100 AArch64: Improve immediate expansion [PR105928] Support immediate expansion of immediates which can be created from 2 MOVKs and a shifted ORR or BIC instruction. Change aarch64_split_dimode_const_store to apply if we save one instruction. This reduces the number of 4-instruction immediates in SPECINT/FP by 5%. gcc/ChangeLog: PR target/105928 * config/aarch64/aarch64.cc (aarch64_internal_mov_immediate) Add support for immediates using shifted ORR/BIC. (aarch64_split_dimode_const_store): Apply if we save one instruction. * config/aarch64/aarch64.md (<LOGICAL:optab>_<SHIFT:optab><mode>3): Make pattern global. gcc/testsuite: PR target/105928 * gcc.target/aarch64/pr105928.c: Add new test. * gcc.target/aarch64/vect-cse-codegen.c: Fix test. ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Bug target/105928] [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca ` (3 preceding siblings ...) 2023-09-18 12:28 ` cvs-commit at gcc dot gnu.org @ 2023-09-18 12:33 ` wilco at gcc dot gnu.org 4 siblings, 0 replies; 6+ messages in thread From: wilco at gcc dot gnu.org @ 2023-09-18 12:33 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105928 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Resolution|--- |FIXED Status|NEW |RESOLVED Target|arm64-*-* |aarch64 Target Milestone|--- |14.0 --- Comment #5 from Wilco <wilco at gcc dot gnu.org> --- Fixed ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-09-18 12:33 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-06-11 20:19 [Bug target/105928] New: [AArch64] 64-bit constants with same high/low halves can use ADD lsl 32 (-Os at least) peter at cordes dot ca 2022-07-05 11:48 ` [Bug target/105928] " rsandifo at gcc dot gnu.org 2023-09-13 13:08 ` wilco at gcc dot gnu.org 2023-09-14 15:26 ` wilco at gcc dot gnu.org 2023-09-18 12:28 ` cvs-commit at gcc dot gnu.org 2023-09-18 12:33 ` wilco at gcc dot gnu.org
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