* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
@ 2022-06-14 6:49 ` ubizjak at gmail dot com
2022-06-14 8:19 ` rguenth at gcc dot gnu.org
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: ubizjak at gmail dot com @ 2022-06-14 6:49 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
Uroš Bizjak <ubizjak at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Last reconfirmed| |2022-06-14
Status|UNCONFIRMED |NEW
Ever confirmed|0 |1
Target Milestone|--- |12.3
CC| |liuhongt at gcc dot gnu.org
--- Comment #1 from Uroš Bizjak <ubizjak at gmail dot com> ---
Instruction does not accept memory operand for operand 3:
(define_insn_and_split
"*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
[(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
(unspec:<ssebytemode>
[(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
(match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
(subreg:<ssebytemode>
(lt:VI48_AVX
(match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
(match_operand:VI48_AVX 4 "const0_operand")) 0)]
UNSPEC_BLENDV))]
The problematic insn is:
(define_insn_and_split "*avx_cmp<mode>3_ltint_not"
[(set (match_operand:VI48_AVX 0 "register_operand")
(vec_merge:VI48_AVX
(match_operand:VI48_AVX 1 "vector_operand")
(match_operand:VI48_AVX 2 "vector_operand")
(unspec:<avx512fmaskmode>
[(subreg:VI48_AVX
(not:<ssebytemode>
(match_operand:<ssebytemode> 3 "vector_operand")) 0)
(match_operand:VI48_AVX 4 "const0_operand")
(match_operand:SI 5 "const_0_to_7_operand")]
UNSPEC_PCMP)))]
which gets split to the above pattern.
In the preparation statements we have:
if (!MEM_P (operands[3]))
operands[3] = force_reg (<ssebytemode>mode, operands[3]);
operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode);
Which won't fly when operand 3 is memory operand...
CC author, g:8fa7216ae0d8
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
2022-06-14 6:49 ` [Bug target/105953] " ubizjak at gmail dot com
@ 2022-06-14 8:19 ` rguenth at gcc dot gnu.org
2022-06-15 5:55 ` cvs-commit at gcc dot gnu.org
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: rguenth at gcc dot gnu.org @ 2022-06-14 8:19 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
Richard Biener <rguenth at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Priority|P3 |P2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
2022-06-14 6:49 ` [Bug target/105953] " ubizjak at gmail dot com
2022-06-14 8:19 ` rguenth at gcc dot gnu.org
@ 2022-06-15 5:55 ` cvs-commit at gcc dot gnu.org
2022-06-15 5:57 ` cvs-commit at gcc dot gnu.org
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-06-15 5:55 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:4b1a827f024234aaf83ecfe90415e88b525d3969
commit r13-1099-g4b1a827f024234aaf83ecfe90415e88b525d3969
Author: liuhongt <hongtao.liu@intel.com>
Date: Tue Jun 14 16:27:04 2022 +0800
Fix ICE in extract_insn, at recog.cc:2791
(In reply to Uroš Bizjak from comment #1)
> Instruction does not accept memory operand for operand 3:
>
> (define_insn_and_split
> "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
> [(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
> (unspec:<ssebytemode>
> [(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
> (match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
> (subreg:<ssebytemode>
> (lt:VI48_AVX
> (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
> (match_operand:VI48_AVX 4 "const0_operand")) 0)]
> UNSPEC_BLENDV))]
>
> The problematic insn is:
>
> (define_insn_and_split "*avx_cmp<mode>3_ltint_not"
> [(set (match_operand:VI48_AVX 0 "register_operand")
> (vec_merge:VI48_AVX
> (match_operand:VI48_AVX 1 "vector_operand")
> (match_operand:VI48_AVX 2 "vector_operand")
> (unspec:<avx512fmaskmode>
> [(subreg:VI48_AVX
> (not:<ssebytemode>
> (match_operand:<ssebytemode> 3 "vector_operand")) 0)
> (match_operand:VI48_AVX 4 "const0_operand")
> (match_operand:SI 5 "const_0_to_7_operand")]
> UNSPEC_PCMP)))]
>
> which gets split to the above pattern.
>
> In the preparation statements we have:
>
> if (!MEM_P (operands[3]))
> operands[3] = force_reg (<ssebytemode>mode, operands[3]);
> operands[3] = lowpart_subreg (<MODE>mode, operands[3],
<ssebytemode>mode);
>
> Which won't fly when operand 3 is memory operand...
>
gcc/ChangeLog:
PR target/105953
* config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg
operands[3].
gcc/testsuite/ChangeLog:
* g++.target/i386/pr105953.C: New test.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
` (2 preceding siblings ...)
2022-06-15 5:55 ` cvs-commit at gcc dot gnu.org
@ 2022-06-15 5:57 ` cvs-commit at gcc dot gnu.org
2022-06-15 7:16 ` crazylht at gmail dot com
2023-03-23 0:16 ` pinskia at gcc dot gnu.org
5 siblings, 0 replies; 7+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2022-06-15 5:57 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by hongtao Liu
<liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:bac09a893145056217b1e9a0054466a770815c43
commit r12-8482-gbac09a893145056217b1e9a0054466a770815c43
Author: liuhongt <hongtao.liu@intel.com>
Date: Tue Jun 14 16:27:04 2022 +0800
Fix ICE in extract_insn, at recog.cc:2791
(In reply to Uroš Bizjak from comment #1)
> Instruction does not accept memory operand for operand 3:
>
> (define_insn_and_split
> "*<sse4_1>_blendv<ssefltmodesuffix><avxsizesuffix>_ltint"
> [(set (match_operand:<ssebytemode> 0 "register_operand" "=Yr,*x,x")
> (unspec:<ssebytemode>
> [(match_operand:<ssebytemode> 1 "register_operand" "0,0,x")
> (match_operand:<ssebytemode> 2 "vector_operand" "YrBm,*xBm,xm")
> (subreg:<ssebytemode>
> (lt:VI48_AVX
> (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
> (match_operand:VI48_AVX 4 "const0_operand")) 0)]
> UNSPEC_BLENDV))]
>
> The problematic insn is:
>
> (define_insn_and_split "*avx_cmp<mode>3_ltint_not"
> [(set (match_operand:VI48_AVX 0 "register_operand")
> (vec_merge:VI48_AVX
> (match_operand:VI48_AVX 1 "vector_operand")
> (match_operand:VI48_AVX 2 "vector_operand")
> (unspec:<avx512fmaskmode>
> [(subreg:VI48_AVX
> (not:<ssebytemode>
> (match_operand:<ssebytemode> 3 "vector_operand")) 0)
> (match_operand:VI48_AVX 4 "const0_operand")
> (match_operand:SI 5 "const_0_to_7_operand")]
> UNSPEC_PCMP)))]
>
> which gets split to the above pattern.
>
> In the preparation statements we have:
>
> if (!MEM_P (operands[3]))
> operands[3] = force_reg (<ssebytemode>mode, operands[3]);
> operands[3] = lowpart_subreg (<MODE>mode, operands[3],
<ssebytemode>mode);
>
> Which won't fly when operand 3 is memory operand...
>
gcc/ChangeLog:
PR target/105953
* config/i386/sse.md (*avx_cmp<mode>3_ltint_not): Force_reg
operands[3].
gcc/testsuite/ChangeLog:
* g++.target/i386/pr105953.C: New test.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
` (3 preceding siblings ...)
2022-06-15 5:57 ` cvs-commit at gcc dot gnu.org
@ 2022-06-15 7:16 ` crazylht at gmail dot com
2023-03-23 0:16 ` pinskia at gcc dot gnu.org
5 siblings, 0 replies; 7+ messages in thread
From: crazylht at gmail dot com @ 2022-06-15 7:16 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC12.2 and trunk.
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug target/105953] [12/13 Regression] ICE in extract_insn, at recog.cc:2791
2022-06-13 17:48 [Bug c++/105953] New: [12/13 Regression] ICE in extract_insn, at recog.cc:2791 gscfq@t-online.de
` (4 preceding siblings ...)
2022-06-15 7:16 ` crazylht at gmail dot com
@ 2023-03-23 0:16 ` pinskia at gcc dot gnu.org
5 siblings, 0 replies; 7+ messages in thread
From: pinskia at gcc dot gnu.org @ 2023-03-23 0:16 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105953
Andrew Pinski <pinskia at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|NEW |RESOLVED
Resolution|--- |FIXED
Target Milestone|12.3 |12.2
--- Comment #5 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
.
^ permalink raw reply [flat|nested] 7+ messages in thread