From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 28CA93858C20; Fri, 1 Jul 2022 01:52:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 28CA93858C20 From: "luoxhu at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106069] [12/13 Regression] wrong code with -O -fno-tree-forwprop -maltivec on ppc64le Date: Fri, 01 Jul 2022 01:52:41 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: luoxhu at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jul 2022 01:52:41 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106069 --- Comment #8 from luoxhu at gcc dot gnu.org --- init-regs: (insn 13 8 17 2 (set (reg:V4SI 141) (vec_select:V4SI (vec_concat:V8SI (reg/v:V4SI 135 [ R2 ]) (reg/v:V4SI 133 [ R0 ])) (parallel [ (const_int 2 [0x2]) (const_int 6 [0x6]) (const_int 3 [0x3]) (const_int 7 [0x7]) ]))) "q.C":22:45 1785 {altivec_vmrglw_direct_v4si} (expr_list:REG_DEAD (reg/v:V4SI 135 [ R2 ]) (expr_list:REG_DEAD (reg/v:V4SI 133 [ R0 ]) (nil)))) (insn 17 13 21 2 (set (reg:V4SI 146) (vec_select:V4SI (vec_concat:V8SI (reg/v:V4SI 136 [ R3 ]) (reg/v:V4SI 134 [ R1 ])) (parallel [ (const_int 2 [0x2]) (const_int 6 [0x6]) (const_int 3 [0x3]) (const_int 7 [0x7]) ]))) "q.C":23:45 1785 {altivec_vmrglw_direct_v4si} (expr_list:REG_DEAD (reg/v:V4SI 136 [ R3 ]) (expr_list:REG_DEAD (reg/v:V4SI 134 [ R1 ]) (nil)))) (insn 21 17 24 2 (set (reg:V4SI 150) (vec_select:V4SI (vec_concat:V8SI (reg:V4SI 146) (reg:V4SI 141)) (parallel [ (const_int 2 [0x2]) (const_int 6 [0x6]) (const_int 3 [0x3]) (const_int 7 [0x7]) ]))) "q.C":26:6 1785 {altivec_vmrglw_direct_v4si} (expr_list:REG_DEAD (reg:V4SI 146) (expr_list:REG_DEAD (reg:V4SI 141) (nil)))) (insn 24 21 25 2 (parallel [ (set (reg:SI 151) (vec_select:SI (reg:V4SI 150) (parallel [ (const_int 3 [0x3]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (nil)) (insn 25 24 26 2 (set (reg:DI 152) (zero_extend:DI (reg:SI 151))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 151) (nil))) (insn 26 25 27 2 (parallel [ (set (reg:SI 153) (vec_select:SI (reg:V4SI 150) (parallel [ (const_int 2 [0x2]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (nil)) (insn 27 26 28 2 (set (reg:DI 154) (zero_extend:DI (reg:SI 153))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 153) (nil))) (insn 28 27 29 2 (parallel [ (set (reg:SI 155) (vec_select:SI (reg:V4SI 150) (parallel [ (const_int 1 [0x1]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (nil)) (insn 29 28 30 2 (set (reg:DI 156) (zero_extend:DI (reg:SI 155))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 155) (nil))) (insn 30 29 31 2 (parallel [ (set (reg:SI 157) (vec_select:SI (reg:V4SI 150) (parallel [ (const_int 0 [0]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (expr_list:REG_DEAD (reg:V4SI 150) (nil))) combine: Trying 13 -> 28: 13: r141:V4SI=3Dvec_select(vec_concat(r164:V4SI,r162:V4SI),parallel) REG_DEAD r164:V4SI 28: {r155:SI=3Dvec_select(r141:V4SI,parallel);clobber scratch;} REG_DEAD r141:V4SI Successfully matched this instruction: (parallel [ (set (reg:SI 155) (vec_select:SI (reg:V4SI 164) (parallel [ (const_int 3 [0x3]) ]))) (clobber (scratch:V4SI)) ]) allowing combination of insns 13 and 28 original costs 4 + 8 =3D 12 replacement cost 8 deferring deletion of insn with uid =3D 13. modifying insn i3 28: {r155:SI=3Dvec_select(r164:V4SI,parallel);clobber scratch;} REG_DEAD r164:V4SI deferring rescan insn with uid =3D 28. (note 7 47 8 2 NOTE_INSN_DELETED) (note 8 7 13 2 NOTE_INSN_FUNCTION_BEG) (note 13 8 17 2 NOTE_INSN_DELETED) (note 17 13 21 2 NOTE_INSN_DELETED) (note 21 17 24 2 NOTE_INSN_DELETED) (insn 24 21 25 2 (parallel [ (set (reg:SI 151) (vec_select:SI (reg:V4SI 162) (parallel [ (const_int 3 [0x3]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (expr_list:REG_DEAD (reg:V4SI 162) (nil))) (note 25 24 26 2 NOTE_INSN_DELETED) (insn 26 25 27 2 (parallel [ (set (reg:SI 153) (vec_select:SI (reg:V4SI 163) (parallel [ (const_int 3 [0x3]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (expr_list:REG_DEAD (reg:V4SI 163) (nil))) (note 27 26 28 2 NOTE_INSN_DELETED) (insn 28 27 29 2 (parallel [ (set (reg:SI 155) (vec_select:SI (reg:V4SI 164) (parallel [ (const_int 3 [0x3]) ]))) (clobber (scratch:V4SI)) ]) "q.C":28:10 1400 {*vsx_extract_si} (expr_list:REG_DEAD (reg:V4SI 164) (nil))) (note 29 28 30 2 NOTE_INSN_DELETED) (insn 33 32 34 2 (set (reg:DI 7 7) (zero_extend:DI (reg:SI 151))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 151) (nil))) (insn 34 33 35 2 (set (reg:DI 6 6) (zero_extend:DI (reg:SI 153))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 153) (nil))) (insn 35 34 36 2 (set (reg:DI 5 5) (zero_extend:DI (reg:SI 155))) "q.C":28:10 16 {zero_extendsidi2} (expr_list:REG_DEAD (reg:SI 155) (nil))) (insn 36 35 37 2 (set (reg:DI 4 4) (zero_extend:DI (reg:SI 157))) "q.C":28:10 16 {zero_extendsidi2} (nil))=