From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 0D01D3857BA6; Thu, 4 Aug 2022 09:21:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D01D3857BA6 From: "rearnsha at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106069] [12/13 Regression] wrong code with -O -fno-tree-forwprop -maltivec on ppc64le Date: Thu, 04 Aug 2022 09:21:47 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.0 X-Bugzilla-Keywords: wrong-code X-Bugzilla-Severity: normal X-Bugzilla-Who: rearnsha at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Aug 2022 09:21:48 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106069 --- Comment #30 from Richard Earnshaw --- (In reply to rsandifo@gcc.gnu.org from comment #29) > (In reply to Segher Boessenkool from comment #28) > > (In reply to rsandifo@gcc.gnu.org from comment #25) > > > - On big-endian targets, vector loads and stores are assumed to put t= he > > > first memory element at the most significant end of the vector regi= ster. > >=20 > > I agree with everything here, except calling this "most significant". = That > > just makes no sense for vectors. It is element 0, but that is not more > > significant than any other element :-) Vectors aren't integers. > Ah, yeah, I should have said =E2=80=9Cmost significant end of the vector = register > if the vector register is viewed as a single integer=E2=80=9D (which is a= n important > difference). The point here was that: >=20 > (a) by default, TI subregs of V4SI registers are assumed to be nops > (and vice versa) >=20 > (b) consequently, TImode loads are assumed to perform the same operation > as V4SI loads >=20 > So endianness assumptions for single integers carry over to like-sized > vector modes. On big-endian, the first element of the V4SI is assumed > to line up with the top 32 bits of a 128-bit integer. >=20 > Although it's possible to force subregs not to be nops (via > targetm.can_change_mode_class), that only really affects changes > to specific hard register classes. The generic rules still apply > to the layout of pseudos. It's not just about when the vector is viewed as an integer. There's also = the case when a vector of NxM is viewed as N/2xM*2 or vice versa, or even for o= ther powers of two. We've tended to call the lane ordering 'little-endian' if t= he lower numbered lane is in the least significant bits of a wider element siz= e, and 'big-endian' if it's in the most significant bits.=