From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 678973830895; Tue, 28 Jun 2022 06:57:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 678973830895 From: "rguenth at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p Date: Tue, 28 Jun 2022 06:57:04 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.1.1 X-Bugzilla-Keywords: ice-on-valid-code, needs-bisection X-Bugzilla-Severity: normal X-Bugzilla-Who: rguenth at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P2 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 12.2 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: component priority Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 28 Jun 2022 06:57:04 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106101 Richard Biener changed: What |Removed |Added ---------------------------------------------------------------------------- Component|rtl-optimization |target Priority|P3 |P2 --- Comment #4 from Richard Biener --- (In reply to Segher Boessenkool from comment #3) > STRICT_LOW_PART is required to contain a SUBREG though. So Trying 23 -> 24: 23: r77:DI=3D[r85:DI] REG_DEAD r85:DI 24: strict_low_part(r71:SI)=3Dr77:DI#4 REG_DEAD r77:DI Successfully matched this instruction: (set (strict_low_part (reg/v:SI 71 [ yyval ])) (mem/f:SI (plus:DI (reg:DI 85) (const_int 4 [0x4])) [2 *_3+4 S4 A32])) allowing combination of insns 23 and 24 just exposes the issue that RTL expansion produces: ;; MEM[(char * *)&yyval] =3D _4; (insn 23 22 24 (set (reg/f:DI 77) (mem/f:DI (reg/f:DI 62 [ _3 ]) [2 *_3+0 S8 A64])) "/tmp/y.tab.i":41= :23 -1 (nil)) (insn 24 23 0 (set (strict_low_part (reg/v:SI 71 [ yyval ])) (subreg:SI (reg/f:DI 77) 4)) "/tmp/y.tab.i":41:23 -1 (nil)) which is emitted via #3 0x0000000001fe5354 in gen_movstrictsi (operand0=3D0x7ffff6a49d20,=20 operand1=3D0x7ffff6a4e438) at insn-emit.cc:11776 #4 0x00000000019163e5 in s390_expand_insv (dest=3D0x7ffff6a4e3f0,=20 op1=3D0x7ffff68c8690, op2=3D0x7ffff68c8690, src=3D0x7ffff6a4e3d8) at /space/rguenther/src/gcc/gcc/config/s390/s390.cc:6530 #5 0x00000000020373a8 in gen_insv (operand0=3D0x7ffff6a4e3f0,=20 operand1=3D0x7ffff68c8690, operand2=3D0x7ffff68c8690, operand3=3D0x7fff= f6a4e3d8) at /space/rguenther/src/gcc/gcc/config/s390/s390.md:4217 ... #8 0x0000000001242f07 in maybe_expand_insn (icode=3DCODE_FOR_insv, nops=3D= 4,=20 ops=3D0x7fffffffc500) at /space/rguenther/src/gcc/gcc/optabs.cc:7998 #9 0x0000000000e43d46 in store_bit_field_using_insv (insv=3D0x7fffffffc7a0= ,=20 op0=3D0x7ffff6a49d20, op0_mode=3DSImode, bitsize=3D32, bitnum=3D32,=20 ; ; movstrictsi instruction pattern(s). ; (define_insn "movstrictsi" [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) (match_operand:SI 1 "general_operand" "d,R,T,t"))] "TARGET_ZARCH" "@ lr\t%0,%1 l\t%0,%1 ly\t%0,%1 ear\t%0,%1" [(set_attr "op_type" "RR,RX,RXY,RRE") (set_attr "type" "lr,load,load,*") (set_attr "cpu_facility" "*,*,longdisp,*") (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) all of which is ancient code ... target issue after all.=