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From: "segher at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p
 since r12-4428-g147ed0184f403b
Date: Wed, 24 Aug 2022 11:57:21 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106101

--- Comment #19 from Segher Boessenkool <segher at gcc dot gnu.org> ---
(In reply to Andreas Krebbel from comment #18)
> (In reply to Segher Boessenkool from comment #17)
> ...
> > Yes, but that says the high 48 bits of the hardware reg are untouched, =
which
> > is not true (only the high 16 of the low 32 are guaranteed unmodified).
>=20
> Right, if the original register mode does not match the mode of the full
> hardreg, we continue to need that mode as the upper bound. So with the
> subreg folding in reload we appear to loose information we need to interp=
ret
> the STRICT_LOW_PART correctly.

Exactly.  This is why strict_low_part of anything else than a subreg is
ill-defined.=