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From: "krebbel at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p
 since r12-4428-g147ed0184f403b
Date: Tue, 19 Jul 2022 11:53:22 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106101

--- Comment #11 from Andreas Krebbel <krebbel at gcc dot gnu.org> ---
I've tried to change our movstrict backend patterns to use a predicate on t=
he
dest operand which enforces a subreg. However, since reload strips the subr=
eg
away when assigning hard regs we end up with a STRICT_LOW_PART of a reg aga=
in.
At least after reload something like this should be acceptable - right?

298r.ira:
(insn 8 16 17 3 (set (strict_low_part (subreg:SI (reg/v:DI 64 [ e ]) 4))
        (const_int 0 [0])) "t.cc":37:17 1485 {movstrictsi}
     (nil))

299r.reload:
(insn 8 16 17 3 (set (strict_low_part (reg:SI 11 %r11 [orig:64 e+4 ] [64]))
        (mem/u/c:SI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0  S4 A32]))
"t.cc":37:17 1485 {movstrictsi}
     (nil))=