From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 859133858282; Mon, 4 Jul 2022 10:56:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 859133858282 From: "jakub at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106180] [13 Regression] ICE in extract_insn, at recog.cc:2791 since r13-1418-g73f942c08deef3 Date: Mon, 04 Jul 2022 10:56:16 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: ice-on-valid-code X-Bugzilla-Severity: normal X-Bugzilla-Who: jakub at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: cc Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Jul 2022 10:56:16 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106180 Jakub Jelinek changed: What |Removed |Added ---------------------------------------------------------------------------- CC| |jakub at gcc dot gnu.org --- Comment #1 from Jakub Jelinek --- The ICE is because (define_expand "vec_unpacks_lo_v4sf" [(set (match_operand:V2DF 0 "register_operand") (float_extend:V2DF (vec_select:V2SF (match_operand:V4SF 1 "vector_operand") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2") used to match the sse2_cvtps2pd both when operands[1] was REG or MEM, but n= ow it doesn't. I think the r13-1418 change was just wrong. It is fine to add a pattern wi= th V2SF input rather than vec_select of first half of V4SF input, but I don't understand why you need to restrict one to memory_operand and the other to register_operand, why vector_operand "vm" can't be used for both. Not doing that ties hands of the register allocator, if something is memory during expansion, it would be always in memory, if something isn't memory, = it couldn't ever be memory. Is your concern not getting a SIGSEGV if first 2 SF elts are at the end of a page and 2 further SF elts are in a non-mapped page?=