[Bug target/106180] [13 Regression] ICE in extract_insn, at recog.cc:2791 since r13-1418-g73f942c08deef3

["wwwhhhyyy333 at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106180

Hongyu Wang <wwwhhhyyy333 at gmail dot com> changed:

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                 CC|                            |wwwhhhyyy333 at gmail dot com

--- Comment #2 from Hongyu Wang <wwwhhhyyy333 at gmail dot com> ---
(In reply to Jakub Jelinek from comment #1)

> I think the r13-1418 change was just wrong.  It is fine to add a pattern
> with V2SF input rather than vec_select of first half of V4SF input, but I
> don't understand why you need to restrict one to memory_operand and the
> other to register_operand, why vector_operand "vm" can't be used for both.
> Not doing that ties hands of the register allocator, if something is memory
> during expansion, it would be always in memory, if something isn't memory,
> it couldn't ever be memory.
> Is your concern not getting a SIGSEGV if first 2 SF elts are at the end of a
> page and 2 further SF elts are in a non-mapped page?

The instruction cvtps2pd takes m64 as memory input, so the original pattern is
not proper since it allows V4SF memory input, although the generated code may
work since for unpack_lo the address is same. The cross-page issue is one of
the potential problem we can meet.

For this pattern, I think we can add

if (MEM_P (operands[1]))
  operands[1] = gen_lowpart (V2SFmode, operands[1])

There are many other unpacks_low expanders allowing memory input, but they
directly falls to cvt instructions. We plan to fix all them recently.