From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 8C6863858C78; Fri, 20 Oct 2023 23:08:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8C6863858C78 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1697843301; bh=2OH8rVzGUn3taC7D+ZZZmh75MB01P4DYaYOnGh+6Mkg=; h=From:To:Subject:Date:In-Reply-To:References:From; b=HKi/37ab7lpP+KbYj/umF9x/HwYDnW9mFs5I+W4iiw0BYoZQxn1UB7UBl5IbrTaAL PAIHk3MIpY+PZ2L8kN+aIPojNnbgCHgJdGgoQl8S+/SE/eIadL/HiBJF7cNjXGIs/x w5PQg/UDwsOUxV++Fm5wNRgi5eOZ/JOb6xZ7WU8g= From: "cvs-commit at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/106245] Failure to optimize (u8)(a << 7) >> 7 pattern to a & 1 Date: Fri, 20 Oct 2023 23:08:20 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: cvs-commit at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106245 --- Comment #3 from CVS Commits --- The master branch has been updated by Roger Sayle : https://gcc.gnu.org/g:e28869670c9879fe7c67caf6cc11af202509ef78 commit r14-4810-ge28869670c9879fe7c67caf6cc11af202509ef78 Author: Roger Sayle Date: Sat Oct 21 00:06:02 2023 +0100 PR 106245: Split (x<<31)>>31 as -(x&1) in i386.md This patch is the backend piece of a solution to PRs 101955 and 106245, that adds a define_insn_and_split to the i386 backend, to perform sign extension of a single (least significant) bit using and $1 then neg. Previously, (x<<31)>>31 would be generated as sall $31, %eax // 3 bytes sarl $31, %eax // 3 bytes with this patch the backend now generates: andl $1, %eax // 3 bytes negl %eax // 2 bytes Not only is this smaller in size, but microbenchmarking confirms that it's a performance win on both Intel and AMD; Intel sees only a 2% improvement (perhaps just a size effect), but AMD sees a 7% win. 2023-10-21 Roger Sayle Uros Bizjak gcc/ChangeLog PR middle-end/101955 PR tree-optimization/106245 * config/i386/i386.md (*extv_1_0): New define_insn_and_sp= lit. gcc/testsuite/ChangeLog PR middle-end/101955 PR tree-optimization/106245 * gcc.target/i386/pr106245-2.c: New test case. * gcc.target/i386/pr106245-3.c: New 32-bit test case. * gcc.target/i386/pr106245-4.c: New 64-bit test case. * gcc.target/i386/pr106245-5.c: Likewise.=