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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106265] RISC-V SPEC2017 507.cactu code bloat due to
 address generation
Date: Thu, 21 Jul 2022 21:21:29 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106265

--- Comment #9 from Vineet Gupta <vineet.gupta at linux dot dev> ---
The redundant Insn 2660 is reload inserted for Insn 1717

 1717: r1871:DI=3Dframe:DI+r2813:DI
    Inserting insn reload before:
 2660: r2814:DI=3D0x1000
 2661: r2813:DI=3Dr2814:DI-0x7e8
      REG_EQUAL 0x818


Insn 1717 in turn is reload inserted for Insn 82

   82: r1870:DI=3Dr1871:DI+r222:DI
      REG_DEAD r222:DI
    Inserting insn reload before:
 1717: r1871:DI=3Dframe:DI+0x28
    Inserting insn reload after:
 1716: r223:DI=3Dr1870:DI


Insn 82 comes from 253r.expand

(insn 80 79 81 5 (set (reg:DI 222 [ _282 ])
        (ashift:DI (reg:DI 74 [ g.1_3 ])
            (const_int 7 [0x7]))) "rhs-cred.cc":44:29 -1
     (nil))
(insn 81 80 82 5 (set (reg:DI 884)
        (plus:DI (reg/f:DI 67 virtual-stack-vars)
            (const_int -8 [0xfffffffffffffff8]))) "rhs-cred.cc":44:29 -1
     (nil))
(insn 82 81 83 5 (set (reg/f:DI 223 [ _283 ])
        (plus:DI (reg:DI 884)
            (reg:DI 222 [ _282 ]))) "rhs-cred.cc":44:29 -1
     (nil))


Stepping thru lra-constraints.cc, curr_insn_transform () is called twice for
Insn 1717 and in the 2nd call (lra_constraints_iter =3D=3D 4), operand is r=
equired
to have a reload (goal_alt_win[2]=3D=3Dfalse) which leads to lra_emit_move =
() ->
riscv_move_integer ()=