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From: "vineet.gupta at linux dot dev" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106265] RISC-V SPEC2017 507.cactu code bloat due to
 address generation
Date: Mon, 11 Jul 2022 23:37:42 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106265

--- Comment #4 from Vineet Gupta <vineet.gupta at linux dot dev> ---
Going back to first dump (upstream 6abe341558a w/o riscv_rtx_costs() adj): =
the
3rd instruction addi is marking a2 REG_DEAD at 315 cprop.hardreg

--->8---- 314r.rnreg

(insn 2663 2662 1714 3 (set (reg:DI 13 a3 [2815])
        (plus:DI (reg:DI 12 a2 [2816])
            (const_int -2024 [0xfffffffffffff818]))) "rhs-cred.cc":42:47 4
{adddi3}
     (expr_list:REG_EQUAL (const_int 2072 [0x818])
        (nil)))


--->8---- 315r.cprop_hardreg

(insn 2663 2662 1714 3 (set (reg:DI 13 a3 [2815])
        (plus:DI (reg:DI 12 a2 [2816])
            (const_int -2024 [0xfffffffffffff818]))) "rhs-cred.cc":42:47 4
{adddi3}
     (expr_list:REG_DEAD (reg:DI 12 a2 [2816])
        (expr_list:REG_EQUAL (const_int 2072 [0x818])
            (nil))))

Not sure if that is the issue or the compiler just deducing that a2 is dead
given that the next instruction sets it up again was introduced much earlie=
r in
300r.reload=