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From: "yangyujie at loongson dot cn" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106462] LRA on mips64el: unable to reload (subreg:SI
 (reg:DI)) constrained by "f"
Date: Thu, 28 Jul 2022 08:01:31 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106462

--- Comment #1 from Yang Yujie <yangyujie at loongson dot cn> ---
The relevant insn template is:

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "register_operand" "=3Df")
        (float:SF (match_operand:SI 1 "register_operand" "f")))]
  "TARGET_HARD_FLOAT"
  "cvt.s.w\t%0,%1"
  [(set_attr "type"     "fcvt")
   (set_attr "mode"     "SF")
   (set_attr "cnv_mode" "I2S")])

It seems that

  (match_operand:SI 1 "register_operand "f")

actually matched (during pass_expand):

  (subreg/s/u:SI (reg/v:DI 209 [orig:197 c ] [197]))

and curr_insn_transform decided to spill the (reg/v:DI 209) pseudo-register
into FP_REGS, which fails because FP registers are only 32-bit-wide.

My question is: should the reload pass handle this by first assigning (reg:=
DI)
into a (64-bit) general-purpose hard register, and then emit a move instruc=
tion
to fill the floating-point-register operand?=