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From: "hubicka at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug rtl-optimization/106518] Exchange/swap aware register allocation (generate xchg in reload)
Date: Thu, 04 Aug 2022 09:53:37 +0000 [thread overview]
Message-ID: <bug-106518-4-XjoLCLyoEi@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-106518-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106518
Jan Hubicka <hubicka at gcc dot gnu.org> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |hubicka at gcc dot gnu.org
--- Comment #2 from Jan Hubicka <hubicka at gcc dot gnu.org> ---
We have xchg patterns in i386.md and corresponding peephole. I used to play
with this long time ago and it was not giving any of performance benefits
becuase xchg at that time was not well optimized in CPUs.
With regstack the main problem is that RTL after reg-stack is inconsistent
since we have no way to explicitly express push/pop operations that renumber
the registers. Some years ago I made patch for that
https://gcc.gnu.org/pipermail/gcc-patches/1999-November/021921.html
Even if you make representation correct register allocation for stack based CPU
is quite different from normal registr allocation.
These days I would more like to see x87 to silently die.
next prev parent reply other threads:[~2022-08-04 9:53 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-03 20:14 [Bug rtl-optimization/106518] New: " roger at nextmovesoftware dot com
2022-08-04 9:32 ` [Bug rtl-optimization/106518] " rguenth at gcc dot gnu.org
2022-08-04 9:53 ` hubicka at gcc dot gnu.org [this message]
2023-04-26 8:11 ` cvs-commit at gcc dot gnu.org
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