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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106532] riscv fails to build enabling ZBA/ZBB/ZBC/ZBS by
 default for 32bit
Date: Fri, 05 Aug 2022 00:40:54 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106532

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Oh why oh why:
  /* Check whether the constant can be loaded in a single
     instruction with zbs extensions.  */
  if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
    return false;


But:
  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
    {
      /* Simply BSETI.  */
      codes[0].code =3D UNKNOWN;
      codes[0].value =3D value;

      /* RISC-V sign-extends all 32bit values that live in a 32bit
         register.  To avoid paradoxes, we thus need to use the
         sign-extended (negative) representation (-1 << 31) for the
         value, if we want to build (1 << 31) in SImode.  This will
         then expand to an LUI instruction.  */
      if (mode =3D=3D SImode && value =3D=3D (HOST_WIDE_INT_1U << 31))
        codes[0].value =3D (HOST_WIDE_INT_M1U << 31);

      return 1;
    }=