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Subject: [Bug target/106550] [rs6000] sub-optimal 64bit constant generation
 for P10
Date: Thu, 15 Sep 2022 06:20:28 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106550

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jiu Fu Guo <guojiufu@gcc.gnu.org>:

https://gcc.gnu.org/g:7a3dfc23a910a47b6c1113b3a28a22858d0b9e7a

commit r13-2679-g7a3dfc23a910a47b6c1113b3a28a22858d0b9e7a
Author: Jiufu Guo <guojiufu@linux.ibm.com>
Date:   Mon Sep 5 13:36:10 2022 +0800

    rs6000: Using pli(paddi) and rotate to build 64bit constants

    Hi,

    Test cases are updated/added, and code is refined as the comments in the
    review for previous version:
    https://gcc.gnu.org/pipermail/gcc-patches/2022-September/600768.html

    As mentioned in PR106550, since pli could support 34bits immediate, we
could
    use less instructions(3insn would be ok) to build 64bits constant with =
pli.

    For example, for constant 0x020805006106003, we could generate it with:
    asm code1:
    pli 9,101736451 (0x6106003)
    sldi 9,9,32
    paddi 9,9, 2130000 (0x0208050)

    or asm code2:
    pli 10, 2130000
    pli 9, 101736451
    rldimi 9, 10, 32, 0

    The asm code2 would be better.
    This patch generates the asm code2 in split1 pass, this patch also supp=
orts
    to generate asm code1 when splitter is only after RA.

    This patch pass boostrap and regtest on ppc64. P10 testing is running.
    Thanks for any comments!

    BR,
    Jeff(Jiufu)

            PR target/106550

    gcc/ChangeLog:

            * config/rs6000/rs6000.cc (rs6000_emit_set_long_const): Use pli.

    gcc/testsuite/ChangeLog:

            * gcc.target/powerpc/pr106550.c: New test.
            * gcc.target/powerpc/pr106550_1.c: New test.=