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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106585] RISC-V: Mis-optimized code gen for zbs
Date: Thu, 11 Aug 2022 15:52:51 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106585

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
One issue is RV32i_zbb produces:
(insn 8 4 9 2 (set (reg:SI 78)
        (ashift:SI (const_int 1 [0x1])
            (subreg:QI (reg/v:SI 76 [ rs2 ]) 0))) "t6.c":3:20 323 {*bsetsi_=
1}
     (expr_list:REG_DEAD (reg/v:SI 76 [ rs2 ])
        (nil)))


While RV64i_zbb does not match:
(insn 7 4 8 2 (set (reg:SI 79)
        (const_int 1 [0x1])) "t6.c":3:20 140 {*movsi_internal}
     (nil))
(insn 8 7 9 2 (set (reg:SI 78)
        (ashift:SI (reg:SI 79)
            (subreg:QI (reg/v:DI 76 [ rs2 ]) 0))) "t6.c":3:20 154 {ashlsi3}
     (expr_list:REG_DEAD (reg:SI 79)
        (expr_list:REG_DEAD (reg/v:DI 76 [ rs2 ])
            (expr_list:REG_EQUAL (ashift:SI (const_int 1 [0x1])
                    (subreg:QI (reg/v:DI 76 [ rs2 ]) 0))
                (nil)))))=