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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106586] riscv32 still broke with zba_zbb_zbc_zbs, ICE in
 do_SUBST in C++ code
Date: Wed, 24 Aug 2022 19:20:40 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106586

--- Comment #14 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The trunk branch has been updated by Andrew Pinski <pinskia@gcc.gnu.org>:

https://gcc.gnu.org/g:2c721ea9473ad7615bb47b66509097bd254bb839

commit r13-2188-g2c721ea9473ad7615bb47b66509097bd254bb839
Author: Andrew Pinski <apinski@marvell.com>
Date:   Mon Aug 15 22:25:13 2022 +0000

    [RISCV] Fix PR 106586: riscv32 vs ZBS

    The problem here is two fold. With RISCV32, 32bit
    const_int are always signed extended to 64bit in HWI.
    So that means for SINGLE_BIT_MASK_OPERAND, it should
    mask off the upper bits to see it is a single bit
    for !TARGET_64BIT.
    Plus there are a few locations which forget to call
    trunc_int_for_mode when generating a SImode constant
    so they are not sign extended correctly for HWI.
    The predicates single_bit_mask_operand and
    not_single_bit_mask_operand need get the same handling
    as SINGLE_BIT_MASK_OPERAND so just use SINGLE_BIT_MASK_OPERAND.

    OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu with
    --with-arch=3DrvNimafdc_zba_zbb_zbc_zbs where N is replaced with 32 or =
64.

    Thanks,
    Andrew Pinski

    gcc/ChangeLog:

            PR target/106586
            * config/riscv/predicates.md (single_bit_mask_operand):
            Use SINGLE_BIT_MASK_OPERAND instead of directly calling pow2p_h=
wi.
            (not_single_bit_mask_operand): Likewise.
            * config/riscv/riscv.cc (riscv_build_integer_1): Don't special =
case
            1<<31 for 32bits as it is already handled.
            Call trunc_int_for_mode on the upper part after the subtraction.
            (riscv_move_integer): Call trunc_int_for_mode before generating
            the integer just make sure the constant has been sign extended
            corectly.
            (riscv_emit_int_compare): Call trunc_int_for_mode after doing t=
he
            addition for the new rhs.
            * config/riscv/riscv.h (SINGLE_BIT_MASK_OPERAND): If !TARGET64B=
IT,
            then mask off the upper 32bits of the HWI as it will be sign
extended.=