[Bug rtl-optimization/106594] [13 Regression] sign-extensions no longer merged into addressing mode

["jakub at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106594

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
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                 CC|                            |jakub at gcc dot gnu.org

--- Comment #20 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
(In reply to rsandifo@gcc.gnu.org from comment #19)
> I completely agree with comment 18.  See:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-September/601472.html
> for some more on a similar theme.
> 
> make_compound_operation_int already has code to convert
> (and (subreg X) (const_int N)) into (zero_extend X) when
> nonzero_bits indicates that that's safe.  I think the AArch64
> regression can be fixed by extending that to:
> 
>   (and (mult (subreg x) (const_int N2)) (const_int N))
>   -> (mult (sign_extend X) (const_int N2))
> 
> for power-of-N2, with the nonzero_bits test adjusted for N2.
> (mult is the canonical form here, since it's part of an address.)
> 
> Testing a patch for that.  Hopefully that should be less
> risky than changing the expand/make_compound_operation
> dance in stage 4.

Complete agreement here, when I was seeing the gcc-patches thread during the
weekend that was exactly what I'd try to do if you haven't posted this comment.
In the nonzero_bits check for this one needs to verify that:
1) low log2(N2) bits don't really matter in N
2) bits above that if zero in N need to correspond to zero in nonzero_bits
after the shift
3) the most significant bit of the SUBREG_REG needs to be clear (so that it
doesn't
matter if it is zero or sign extension)