From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 8F20B3858C52; Fri, 12 Aug 2022 12:44:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8F20B3858C52 From: "tnfchris at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/106594] [13 Regression] sign-extensions no longer merged into addressing mode Date: Fri, 12 Aug 2022 12:44:25 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: tnfchris at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: 13.0 X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 12:44:25 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106594 --- Comment #2 from Tamar Christina --- (In reply to Richard Biener from comment #1) > I believe this was some match.pd simplification - why does this affect the > addressing mode? Is the IVOPTs result different or does it differ later? The results in IVOpts don't change aside from the changes mentioned above. = It looks like this was previously being matched in RTL through combine. Before we had (insn 25 24 26 4 (set (reg:DI 118) (sign_extend:DI (reg:SI 117))) "/app/example.c":12:35 109 {*extendsidi2_aarch64} (expr_list:REG_DEAD (reg:SI 117) (nil))) (insn 26 25 27 4 (set (reg:SI 119 [ constellation_64qam[_6] ]) (mem/u:SI (plus:DI (mult:DI (reg:DI 118) (const_int 4 [0x4])) (reg/f:DI 120)) [1 constellation_64qam[_6]+0 S4 A32])) "/app/example.c":12:14 52 {*movsi_aarch64} Trying 25 -> 26: 25: r118:DI=3Dsign_extend(r117:SI) REG_DEAD r117:SI 26: r119:SI=3D[r118:DI*0x4+r120:DI] REG_DEAD r118:DI REG_EQUAL [r118:DI*0x4+`constellation_64qam'] Successfully matched this instruction: (set (reg:SI 119 [ constellation_64qamD.3590[_6] ]) (mem/u:SI (plus:DI (mult:DI (sign_extend:DI (reg:SI 117)) (const_int 4 [0x4])) (reg/f:DI 120)) [1 constellation_64qamD.3590[_6]+0 S4 A32])) allowing combination of insns 25 and 26 original costs 4 + 16 =3D 20 replacement cost 16 deferring deletion of insn with uid =3D 25. modifying insn i3 26: r119:SI=3D[sign_extend(r117:SI)*0x4+r120:DI] REG_DEAD r117:SI deferring rescan insn with uid =3D 26. now, instead we have (insn 24 23 25 4 (set (reg:DI 116) (sign_extend:DI (reg:SI 115))) "/app/example.c":12:35 126 {*extendsidi2_aarch64} (expr_list:REG_DEAD (reg:SI 115) (nil))) (insn 25 24 26 4 (set (reg:SI 117 [ constellation_64qam[_5] ]) (mem/u:SI (plus:DI (mult:DI (reg:DI 116) (const_int 4 [0x4])) (reg/f:DI 118)) [1 constellation_64qam[_5]+0 S4 A32])) "/app/example.c":12:14 52 {*movsi_aarch64} Trying 24 -> 25: 24: r116:DI=3Dsign_extend(r115:SI) REG_DEAD r115:SI 25: r117:SI=3D[r116:DI*0x4+r118:DI] REG_DEAD r116:DI REG_EQUAL [r116:DI*0x4+`constellation_64qam'] Failed to match this instruction: (set (reg:SI 117 [ constellation_64qamD.3641[_5] ]) (mem/u:SI (plus:DI (and:DI (mult:DI (subreg:DI (reg:SI 115) 0) (const_int 4 [0x4])) (const_int 252 [0xfc])) (reg/f:DI 118)) [1 constellation_64qamD.3641[_5]+0 S4 A32])) where the sign extend has suddenly turned into an and. I don't know why though, the two input RTLs look identical to me.=