From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 8197B3858C2C; Fri, 12 Aug 2022 11:23:55 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8197B3858C2C From: "tnfchris at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug tree-optimization/106594] New: [13 Regression] sign-extensions no longer merged into addressing mode Date: Fri, 12 Aug 2022 11:23:55 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: new X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: tree-optimization X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: tnfchris at gcc dot gnu.org X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: bug_id short_desc product version bug_status keywords bug_severity priority component assigned_to reporter target_milestone cf_gcctarget Message-ID: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 X-BeenThere: gcc-bugs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-bugs mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Aug 2022 11:23:55 -0000 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106594 Bug ID: 106594 Summary: [13 Regression] sign-extensions no longer merged into addressing mode Product: gcc Version: 13.0 Status: UNCONFIRMED Keywords: missed-optimization Severity: normal Priority: P3 Component: tree-optimization Assignee: unassigned at gcc dot gnu.org Reporter: tnfchris at gcc dot gnu.org Target Milestone: --- Target: aarch64* Since around the 5th of August (need to bisect) we no longer generate addressing modes on load merging the sign extends. The following example: extern const int constellation_64qam[64]; void foo(int nbits, const char *p_src, int *p_dst) { while (nbits > 0U) { char first =3D *p_src++; char index1 =3D ((first & 0x3) << 4) | (first >> 4); *p_dst++ =3D constellation_64qam[index1]; nbits--; } } used to generate orr w3, w4, w3, lsr 4 ldr w3, [x6, w3, sxtw 2] and now generates: orr w0, w4, w0, lsr 4 sxtw x0, w0 ldr w0, [x6, x0, lsl 2] at -O2 (-O1 seems to still be fine). This is causing a regression in perf = in some of our libraries. Looks like there's a change in how the operation is expressed. It used to = be first_17 =3D *p_src_28; _1 =3D (int) first_17; _2 =3D _1 << 4; _3 =3D (signed char) _2; where the shift is done as an int, whereas now it's first_16 =3D *p_src_27; first.1_1 =3D (signed char) first_16; _2 =3D first.1_1 << 4;=