From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id F04753858D28; Wed, 2 Nov 2022 01:35:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F04753858D28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667352906; bh=fJti+Qsxds+8KUbdqJw+vcVa0/2M/Ic+jBMNJ70X108=; h=From:To:Subject:Date:In-Reply-To:References:From; b=AJUE+2ofuY0s229lbWEYx+f5DkoVh5hrdSXrbkqQErysKj+4NMff9BvY0ekTfMaGC cffay0BoBCeV3KBfIO5QGtW7nVWnZljRB56sUwqF8lkJQXcRvK9kX6Oo507278FqVO 8n5moC1Oyz6aQ3hil10/jf5HDTHarmv2ioQHWcy4= From: "pinskia at gcc dot gnu.org" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106602] riscv: suboptimal codegen for zero_extendsidi2_shifted w/o bitmanip Date: Wed, 02 Nov 2022 01:35:06 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 13.0 X-Bugzilla-Keywords: missed-optimization X-Bugzilla-Severity: normal X-Bugzilla-Who: pinskia at gcc dot gnu.org X-Bugzilla-Status: NEW X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602 --- Comment #16 from Andrew Pinski --- (In reply to Vineet Gupta from comment #14) > (In reply to Jeffrey A. Law from comment #13) > > Trying 7, 8, 9 -> 10: > > 7: r140:DI=3D0x1 > > 8: r141:DI=3Dr140:DI<<0x26 > > REG_DEAD r140:DI > > REG_EQUAL 0x4000000000 > > 9: r139:DI=3Dr141:DI-0x40 > > REG_DEAD r141:DI > > REG_EQUAL 0x3fffffffc0 > > 10: r137:DI=3Dr138:DI&r139:DI > > REG_DEAD r139:DI > > REG_DEAD r138:DI > > Failed to match this instruction: > > (set (reg:DI 137) > > (and:DI (reg:DI 138) > > (const_int 274877906880 [0x3fffffffc0]))) > >=20 > >=20 > > That's what we're looking for. I think I had a wrong switch somewhere.= =20 > > Match that with a define_split and you should be good to go. >=20 > I think you are missing the original left shift 6. > So insn 6 from my dumps is important if we are to match > zero_extendsidi2_shifted which matches and+shift (iff 3>>2=3D=3D0xfffffff= f). >=20 > But it feels like you agree on using REG_EQUAL note (if avail) to created > merged pattern in try_combine() as opposed to my original thinking of only > doing it if regular pattern match failed. So what Jeff is saying is you just need a define_split which matches that f= inal set. Something like: (define_split [(set (match_operand:DI 0 "register_operand" "") (and:SI (match_operand:SI 1 "register_operand" "") (match_operand:SI 2 "shifted_mask_operand" "")))] "" [(set (match_operand:DI 0 ....=