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Subject: [Bug target/106602] riscv: suboptimal codegen for
 zero_extendsidi2_shifted w/o bitmanip
Date: Tue, 27 Dec 2022 23:31:08 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602

--- Comment #26 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:2e886eef7f2b5aadb00171af868f0895b647c3a4

commit r13-4907-g2e886eef7f2b5aadb00171af868f0895b647c3a4
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Tue Dec 27 18:29:25 2022 -0500

    RISC-V: Produce better code with complex constants [PR95632] [PR106602]

    gcc/Changelog:
            PR target/95632
            PR target/106602
            * config/riscv/riscv.md: New pattern to simulate complex
            const_int loads.

    gcc/testsuite/ChangeLog:
            * gcc.target/riscv/pr95632.c: New test.
            * gcc.target/riscv/pr106602.c: New test.=