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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for
 zero_extendsidi2_shifted w/o bitmanip
Date: Wed, 19 Apr 2023 02:41:28 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602

--- Comment #29 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-13 branch has been updated by Palmer Dabbelt
<palmer@gcc.gnu.org>:

https://gcc.gnu.org/g:a252c73b1f2b920d8a2ff2e8ca59989e06652fbb

commit r13-7220-ga252c73b1f2b920d8a2ff2e8ca59989e06652fbb
Author: Palmer Dabbelt <palmer@rivosinc.com>
Date:   Mon Apr 17 11:20:42 2023 -0700

    RISC-V: Clean up the pr106602.c testcase

    The test case that was added is rv64i-specific, as there's better ways
    to generate this code on rv32i (where the long/int cast is a NOP) and on
    rv64i_zba (where we have word shifts).  This renames the original test
    case and adds two more for those targets.

    gcc/testsuite/ChangeLog:
            PR target/106602
            * gcc.target/riscv/pr106602.c: Moved to...
            * gcc.target/riscv/pr106602-rv64i.c: ...here.
            * gcc.target/riscv/pr106602-rv32i.c: New test.
            * gcc.target/riscv/pr106602-rv64i_zba.c: New test.

    (cherry picked from commit 8c010f6fe5ebe80d2e054b31e04ae0e9f12ae368)=