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From: "law at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for
 zero_extendsidi2_shifted w/o bitmanip
Date: Wed, 02 Nov 2022 01:31:17 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602

--- Comment #15 from Jeffrey A. Law <law at gcc dot gnu.org> ---
THe hope is the shift 6 combines with the first shift you emit for

(set (reg:DI 137)
    (and:DI (reg:DI 138)
        (const_int 274877906880 [0x3fffffffc0])))

Conceptually this is similar to creating bridge patterns for the combiner.=