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From: "law at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for
 zero_extendsidi2_shifted w/o bitmanip
Date: Wed, 02 Nov 2022 01:03:38 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602

--- Comment #13 from Jeffrey A. Law <law at gcc dot gnu.org> ---

Trying 7, 8, 9 -> 10:
    7: r140:DI=3D0x1
    8: r141:DI=3Dr140:DI<<0x26
      REG_DEAD r140:DI
      REG_EQUAL 0x4000000000
    9: r139:DI=3Dr141:DI-0x40
      REG_DEAD r141:DI
      REG_EQUAL 0x3fffffffc0
   10: r137:DI=3Dr138:DI&r139:DI
      REG_DEAD r139:DI
      REG_DEAD r138:DI
Failed to match this instruction:
(set (reg:DI 137)
    (and:DI (reg:DI 138)
        (const_int 274877906880 [0x3fffffffc0])))


That's what we're looking for.  I think I had a wrong switch somewhere.  Ma=
tch
that with a define_split and you should be good to go.=