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From: "vineetg at rivosinc dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106602] riscv: suboptimal codegen for
 zero_extendsidi2_shifted w/o bitmanip
Date: Wed, 02 Nov 2022 01:24:33 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106602

--- Comment #14 from Vineet Gupta <vineetg at rivosinc dot com> ---
(In reply to Jeffrey A. Law from comment #13)
> Trying 7, 8, 9 -> 10:
>     7: r140:DI=3D0x1
>     8: r141:DI=3Dr140:DI<<0x26
>       REG_DEAD r140:DI
>       REG_EQUAL 0x4000000000
>     9: r139:DI=3Dr141:DI-0x40
>       REG_DEAD r141:DI
>       REG_EQUAL 0x3fffffffc0
>    10: r137:DI=3Dr138:DI&r139:DI
>       REG_DEAD r139:DI
>       REG_DEAD r138:DI
> Failed to match this instruction:
> (set (reg:DI 137)
>     (and:DI (reg:DI 138)
>         (const_int 274877906880 [0x3fffffffc0])))
>=20
>=20
> That's what we're looking for.  I think I had a wrong switch somewhere.=20
> Match that with a define_split and you should be good to go.

I think you are missing the original left shift 6.
So insn 6 from my dumps is important if we are to match
zero_extendsidi2_shifted which matches and+shift (iff 3>>2=3D=3D0xffffffff).

But it feels like you agree on using REG_EQUAL note (if avail) to created
merged pattern in try_combine() as opposed to my original thinking of only
doing it if regular pattern match failed.=