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Subject: [Bug target/106635] AARCH64 STUR instruction causes bus error
Date: Tue, 16 Aug 2022 11:15:54 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106635

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |INVALID
             Status|WAITING                     |RESOLVED

--- Comment #5 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Your original code contains (after stripping out the volatile):
    u32 temp_32 =3D (u32)status_data_base_addr;
    *dst++ =3D temp_32;
    data_length++;

    if(sizeof(addr_t) =3D=3D 8) {
      *dst++ =3D (u32)(((u64)status_data_base_addr)>>32);
      data_length++;
    }

Which of course on a 64-bit machine simplifies to=20

    u32 temp_32 =3D (u32)status_data_base_addr;
    *dst++ =3D temp_32;
    data_length++;

    *dst++ =3D (u32)(((u64)status_data_base_addr)>>32);
    data_length++;

And which the compiler then further simplifies to=20

   *([unaligned]u64*)dst =3D status_data_base_addr;
   data_length +=3D 2;
   dst +=3D 2;

If the location that dst points to is in normal, cachable, memory, then this
will be fine.  But if you're writing to non-cachable memory, then you might=
 get
a trap.

the correct fix is to mark dst as volatile in this case.

void CWLCollectReadRegData(volatile u32* dst,u16 reg_start, u32 reg_length,=
u32*
total_length, addr_t status_data_base_addr)=