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From: "xgchenshy at 126 dot com" <gcc-bugzilla@gcc.gnu.org>
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Subject: [Bug target/106635] AARCH64 STUR instruction causes bus error
Date: Wed, 17 Aug 2022 02:26:12 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106635

--- Comment #6 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Richard Earnshaw from comment #5)
> Your original code contains (after stripping out the volatile):
>     u32 temp_32 =3D (u32)status_data_base_addr;
>     *dst++ =3D temp_32;
>     data_length++;
>=20=20
>     if(sizeof(addr_t) =3D=3D 8) {
>       *dst++ =3D (u32)(((u64)status_data_base_addr)>>32);
>       data_length++;
>     }
>=20
> Which of course on a 64-bit machine simplifies to=20
>=20
>     u32 temp_32 =3D (u32)status_data_base_addr;
>     *dst++ =3D temp_32;
>     data_length++;
>=20=20
>     *dst++ =3D (u32)(((u64)status_data_base_addr)>>32);
>     data_length++;
>=20
> And which the compiler then further simplifies to=20
>=20
>    *([unaligned]u64*)dst =3D status_data_base_addr;
>    data_length +=3D 2;
>    dst +=3D 2;
>=20
> If the location that dst points to is in normal, cachable, memory, then t=
his
> will be fine.  But if you're writing to non-cachable memory, then you mig=
ht
> get a trap.
Thanks Very much for the explaination, Can you tell me why unaligned access
only  works in normal cachable memory? where does this constraint come from=
?=20

>=20
> the correct fix is to mark dst as volatile in this case.
>=20
> void CWLCollectReadRegData(volatile u32* dst,u16 reg_start, u32
> reg_length,u32*
> total_length, addr_t status_data_base_addr)=