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From: "xgchenshy at 126 dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106635] AARCH64 STUR instruction causes bus error
Date: Wed, 17 Aug 2022 06:37:16 +0000	[thread overview]
Message-ID: <bug-106635-4-owlUn884hV@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-106635-4@http.gcc.gnu.org/bugzilla/>

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106635

--- Comment #10 from Xiaoguang <xgchenshy at 126 dot com> ---
(In reply to Xiaoguang from comment #9)
> (In reply to Andrew Pinski from comment #8)
> > In ARM Armv8, for A-profile architecture (ARM DDI 0487G.b (ID072021)): 
> > 
> > From section B2.5.2 Alignment of data accesses:
> > 
> > An unaligned access to any type of Device memory causes an Alignment fault.
> > 
> > Unaligned accesses to Normal memory
> 
> Yeah, I also find such description, my memory type is uncachable normal
> memory, but not device memory
> I use mmap to get the virtual address with an O_SYNC in fd

Also I didn't see whether normal memory cacheable or not impacts alignment
access , besides, STUR instruction has unscaled imm offset, it should support
unaligned access on normal memory, no matter cached or not,and my X0 is normal
memory so I'm still confusing why it fails, please correct my if my
understanding is wrong. thanks very much

      parent reply	other threads:[~2022-08-17  6:37 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-16  6:51 [Bug c/106635] New: " xgchenshy at 126 dot com
2022-08-16  8:04 ` [Bug target/106635] " rguenth at gcc dot gnu.org
2022-08-16  8:34 ` xgchenshy at 126 dot com
2022-08-16  8:35 ` xgchenshy at 126 dot com
2022-08-16  8:36 ` xgchenshy at 126 dot com
2022-08-16 11:15 ` rearnsha at gcc dot gnu.org
2022-08-17  2:26 ` xgchenshy at 126 dot com
2022-08-17  2:32 ` pinskia at gcc dot gnu.org
2022-08-17  2:50 ` pinskia at gcc dot gnu.org
2022-08-17  3:27 ` xgchenshy at 126 dot com
2022-08-17  6:37 ` xgchenshy at 126 dot com [this message]

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