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From: "pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/106818] riscv produces bad low_sum while doing expansion
 of strict aligned stores/load
Date: Fri, 21 Oct 2022 16:33:49 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106818

--- Comment #12 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
MIPS also does the correct thing (it has store left/right):

(insn 10 9 11 (set (reg/f:SI 196)
        (lo_sum:SI (reg:SI 194)
            (symbol_ref:SI ("array") [flags 0x40]  <var_decl 0x7f1c8d421510
array>))) "/app/example.cpp":10:10 -1
     (nil))

(insn 11 10 12 (set (mem/c:BLK (lo_sum:SI (reg:SI 194)
                (symbol_ref:SI ("array") [flags 0x40]  <var_decl 0x7f1c8d42=
1510
array>)) [1 MEM[(struct sss_t *)&array].i+0 S4 A8])
        (unspec:BLK [
                (reg:SI 195)
                (mem/c:QI (lo_sum:SI (reg:SI 194)
                        (symbol_ref:SI ("array") [flags 0x40]  <var_decl
0x7f1c8d421510 array>)) [1 MEM[(struct sss_t *)&array].i+0 S1 A8])
            ] UNSPEC_STORE_LEFT)) "/app/example.cpp":10:10 -1
     (nil))

(insn 12 11 0 (set (mem/c:BLK (lo_sum:SI (reg:SI 194)
                (symbol_ref:SI ("array") [flags 0x40]  <var_decl 0x7f1c8d42=
1510
array>)) [1 MEM[(struct sss_t *)&array].i+0 S4 A8])
        (unspec:BLK [
                (reg:SI 195)
                (mem/c:QI (plus:SI (reg/f:SI 196)
                        (const_int 3 [0x3])) [1 MEM[(struct sss_t *)&array]=
.i+3
S1 A8])
                (mem/c:BLK (lo_sum:SI (reg:SI 194)
                        (symbol_ref:SI ("array") [flags 0x40]  <var_decl
0x7f1c8d421510 array>)) [1 MEM[(struct sss_t *)&array].i+0 S4 A8])
            ] UNSPEC_STORE_RIGHT)) "/app/example.cpp":10:10 -1
     (nil))

But you can see the the plus of reg196 and 3 and reg196 was set to the low_=
sum
and such.=