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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/106888] [RISCV] Negative optimization that
 excess andi instructions are generated  in gcc.dg/pr90838.c
Date: Sat, 20 May 2023 02:55:20 +0000
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106888

--- Comment #11 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:9000da00dd70988f30d43806bae33b22ee6b9904

commit r14-1006-g9000da00dd70988f30d43806bae33b22ee6b9904
Author: Raphael Moreira Zinsly <rzinsly@ventanamicro.com>
Date:   Fri May 19 20:54:34 2023 -0600

    RISC-V: Fix CTZ unnecessary sign extension [PR #106888]

    Changes since v1:
            - Remove subreg from operand 1.

    -- >8 --

    We were not able to match the CTZ sign extend pattern on RISC-V
    because it gets optimized to zero extend and/or to ANDI patterns.
    For the ANDI case, combine scrambles the RTL and generates the
    extension by using subregs.

    gcc/ChangeLog:
            PR target/106888
            * config/riscv/bitmanip.md
            (<bitmanip_optab>disi2): Match with any_extend.
            (<bitmanip_optab>disi2_sext): New pattern to match
            with sign extend using an ANDI instruction.

    gcc/testsuite/ChangeLog:
            PR target/106888
            * gcc.target/riscv/pr106888.c: New test.
            * gcc.target/riscv/zbbw.c: Check for ANDI.=