From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 48) id 5307B3858C52; Sun, 9 Jul 2023 05:06:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5307B3858C52 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1688879195; bh=5tOSi1tfpdJCDJk4b344JEZW1Vzy0HaECSxC1yj+pHc=; h=From:To:Subject:Date:In-Reply-To:References:From; b=N/6mKg+fTEIDeXcUiRtwbM5QgV1UFOjh1tVprxks0P8Eps38vwjKGk9SRJbsgc4tM nNs1PdgIL2jVxzwRt7fbs4Q+I8bppM3fJTTzjwMMfe3sgB+ZU9lueoKrQqwKqyQ+Xn B+k8L3iDDI4ZLJL9DhM7P/EeYRA0qVWNZAWneKDY= From: "npiggin at gmail dot com" To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106895] powerpc64 unable to specify even/odd register pairs in extended inline asm Date: Sun, 09 Jul 2023 05:06:34 +0000 X-Bugzilla-Reason: CC X-Bugzilla-Type: changed X-Bugzilla-Watch-Reason: None X-Bugzilla-Product: gcc X-Bugzilla-Component: target X-Bugzilla-Version: 12.2.0 X-Bugzilla-Keywords: inline-asm X-Bugzilla-Severity: enhancement X-Bugzilla-Who: npiggin at gmail dot com X-Bugzilla-Status: UNCONFIRMED X-Bugzilla-Resolution: X-Bugzilla-Priority: P3 X-Bugzilla-Assigned-To: unassigned at gcc dot gnu.org X-Bugzilla-Target-Milestone: --- X-Bugzilla-Flags: X-Bugzilla-Changed-Fields: Message-ID: In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Bugzilla-URL: http://gcc.gnu.org/bugzilla/ Auto-Submitted: auto-generated MIME-Version: 1.0 List-Id: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D106895 --- Comment #13 from Nicholas Piggin --- (In reply to Segher Boessenkool from comment #12) > > I guess that would be annoying if you couldn't have modifiers on constr= aints >=20 > There is no such thing as "operand modifiers". There are *output* modifi= ers: > they change how an operand is *printed*, they do not change the operand in > any > way, shape, or form. No I mean like x, y, z for different register pairs, or Pn where n=3D0..4, = eI, eP, eQ for different immediates. If they're practically just implemented as another constraint, what is real= ly the big deal with adding a even/odd GPR pair constraint anyway? You say it's 2^T^N additional constraints. As far as I can tell it turns out to be one e= xtra constrain, or maybe 2 if you need one that excludes r0.=20 >=20 > > or a bad algorithm for working them out. Fair enough. >=20 > No idea what you mean here? If you can't deal well with more constraints. >=20 > > > > or why TI doesn't work but PTI apparently would, > > >=20 > > > Because this is exactly what PTImode is *for*! > >=20 > > Right I accept it is, I meant I just would not have been able to work i= t out > > (assuming if PTI was documented it would be "Partial Tetra Integer" and= be > > no more useful than the other P?I type documentation. >=20 > For the rs6000 port, multi-register operands are not restricted to aligned > register numbers ("even/odd pairs"). (Some other ports do have this). We > use > the existing PTI mode for that (it also can be allocated in GPRs only, ne= ver > in > VSRs, unlike TImode). >=20 > "Partial" does not have much meaning here. A minority of ports use parti= al > integer words for what they were introduced for originally: modes that are > smaller than a full register, say, a 24-bit mode when registers are 32 bi= ts. >=20 > We use it as another integer mode that is the same size. It is unfortuna= te > that we still have to resort to such tricks. Okay that explains it, thank you.=