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From: "zhongyunde at huawei dot com" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug c/107090] New: [aarch64] sequence logic should be combined with
 mul and umulh
Date: Thu, 29 Sep 2022 17:51:35 +0000
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X-Bugzilla-Product: gcc
X-Bugzilla-Component: c
X-Bugzilla-Version: 13.0
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X-Bugzilla-Who: zhongyunde at huawei dot com
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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=3D107090

            Bug ID: 107090
           Summary: [aarch64] sequence logic should be combined with mul
                    and umulh
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zhongyunde at huawei dot com
  Target Milestone: ---

* test case: https://godbolt.org/z/x5jMhqW8s
```
#  define BN_BITS4        32
#  define BN_MASK2        (0xffffffffffffffffL)
#  define BN_MASK2l       (0xffffffffL)
#  define BN_MASK2h       (0xffffffff00000000L)
#  define BN_MASK2h1      (0xffffffff80000000L)
#  define LBITS(a)        ((a)&BN_MASK2l)
#  define HBITS(a)        (((a)>>BN_BITS4)&BN_MASK2l)
#  define L2HBITS(a)      (((a)<<BN_BITS4)&BN_MASK2)

void mul64(unsigned long in0, unsigned long in1,
           unsigned long &l, unsigned long &h) {
    unsigned long m, m1, lt, ht, bl, bh;
    lt =3D LBITS(in0);
    ht =3D HBITS(in0);
    bl =3D LBITS(in1);
    bh =3D HBITS(in1);
    m  =3D bh * lt;
    lt =3D bl * lt;
    m1 =3D bl * ht;
    ht =3D bh * ht;
    m  =3D (m + m1) & BN_MASK2;
    if (m < m1) ht +=3D L2HBITS((unsigned long)1);
    ht +=3D HBITS(m);
    m1 =3D L2HBITS(m);
    lt =3D (lt + m1) & BN_MASK2; if (lt < m1) ht++;
    l  =3D lt;
    h  =3D ht;
}
```
* The above source is equel to an mull operater for two 64bits integer vaul=
es,
so it should be fold to similar assemble
```
   mul   x8,x1,x0
   umulh x9,x0,x1
   str   x8,[x2]
   str   x9,[x3]
   ret
```=